GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-M 

Separate NO_XIP_EARLY_STAGES from loading FSP-M into cache-as-RAM.
Quark executes romstage directly from the SPI flash part (in-place),
but loads FSP-M into ESRAM.  This split occurs because ESRAM is too
small to hold everything while debugging.

Platforms executing FSP-M directly from the SPI flash need to select
FSP_M_XIP.

TEST=Build and run on Galileo Gen2.

Change-Id: Ib5313ae96dcec101510e82438b1889d315569696
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15848
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy 2016-07-21 11:16:39 -07:00
parent e2422e38ce
commit 27cd96a661
2 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/drivers/intel/fsp2_0/Kconfig
View File

@ -32,4 +32,10 @@ config FSP_S_FILE
help
The path and filename of the Intel FSP-S binary for this platform.
config FSP_M_XIP
bool "Is FSP-M XIP"
default n
help
Select this value when FSP-M is execute-in-place.
endif

2
src/drivers/intel/fsp2_0/memory_init.c
View File

@ -303,7 +303,7 @@ enum fsp_status fsp_memory_init(bool s3wake)
_car_relocatable_data_end - _car_region_start, 0);
memranges_insert(&memmap, (uintptr_t)_program, _program_size, 0);
if (IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES))
if (!IS_ENABLED(CONFIG_FSP_M_XIP))
status = load_fspm_mem(&hdr, &file_data, &memmap);
else
status = load_fspm_xip(&hdr, &file_data);