arch/riscv: Align trap_entry to 4 bytes, as required by spec

The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.

Add the necessary alignment directive before trap_entry.

Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/arch/riscv/trap_util.S

@@ -109,6 +109,7 @@
   .text
 
     .global  trap_entry
+    .align 2	# four byte alignment, as required by mtvec
 trap_entry:
   csrw mscratch, sp