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soc/intel/skylake: Include some microcode blobs

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This included the microcode for some CPUID's found in
soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release
SKU's)

The amount of FIT entries needed is currently 7 so setting
CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all.

Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2018-01-05 17:51:46 +01:00 committed by Nico Huber
parent 1f64e6aa85
commit 27d3f71f1d
2 changed files with 15 additions and 1 deletions
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4
src/soc/intel/skylake/Kconfig
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@ -77,6 +77,10 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select UDELAY_TSC
config CPU_INTEL_NUM_FIT_ENTRIES
int
default 10
config MAINBOARD_USES_FSP2_0
bool
default n

12
src/soc/intel/skylake/Makefile.inc
View file

@ -82,7 +82,17 @@ postcar-y += spi.c
postcar-y += i2c.c
postcar-$(CONFIG_UART_DEBUG) += uart.c
# cpu_microcode_bins += ???
# Skylake D0
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin
# Skylake H Q0
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin
# Kabylake H0, Y0
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin
# Kabylake HB0
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin
# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8)
# since those are probably pre-release samples.
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include