vendorcode/intel/.../skylake: Update FspUpdVpd.h to v1.8.1
This corresponds with the changes that have already gone into the soc/intel/skylake chip.h file and is needed to get skylake platforms building again. Change-Id: I15bfee4eff50d6632659953ec8f97a39d8810db3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13022 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth
parent
5d6929b1d7
commit
27d71da71a
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@ -92,6 +92,34 @@ typedef struct {
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#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
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///
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/// USB Overcurrent pins definition, the values match the setting of PCH EDS, please refer to PCH EDS for more details
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///
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typedef enum {
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UsbOverCurrentPin0 = 0,
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UsbOverCurrentPin1,
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UsbOverCurrentPin2,
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UsbOverCurrentPin3,
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UsbOverCurrentPin4,
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UsbOverCurrentPin5,
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UsbOverCurrentPin6,
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UsbOverCurrentPin7,
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UsbOverCurrentPinSkip,
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UsbOverCurrentPinMax
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} USB_OVERCURRENT_PIN;
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///
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/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
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///
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typedef struct {
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UINT8 Revision;
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UINT8 Rsvd[3];
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UINT16 MeChipInitCrc;
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UINT16 BiosChipInitCrc;
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} CHIPSET_INIT_INFO;
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typedef struct {
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UINT8 DimmId;
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UINT32 SizeInMb;
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@ -254,15 +282,9 @@ typedef struct {
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**/
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UINT8 ProbelessTrace;
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/** Offset 0x0093 - Enable LAN
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Enable/disable LAN controller.
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$EN_DIS
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/** Offset 0x0093
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**/
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UINT8 EnableLan;
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/** Offset 0x0094
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**/
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UINT16 UnusedUpdSpace2;
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UINT8 UnusedUpdSpace2[3];
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/** Offset 0x0096 - Enable Trace Hub
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Enable/disable Trace Hub function.
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@ -270,20 +292,9 @@ typedef struct {
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**/
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UINT8 EnableTraceHub;
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/** Offset 0x0097 - Enable PCIE RP
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Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
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/** Offset 0x0097
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**/
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UINT8 PcieRpEnable[20];
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/** Offset 0x00AB - Enable PCIE RP CLKREQ Support
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Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
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**/
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UINT8 PcieRpClkReqSupport[20];
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/** Offset 0x00BF - Configure CLKREQ Number
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Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.
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**/
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UINT8 PcieRpClkReqNumber[20];
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UINT8 UnusedUpdSpace3[60];
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/** Offset 0x00D3 - Internal Graphics Pre-allocated Memory
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Size of memory preallocated for internal graphics.
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@ -329,7 +340,7 @@ typedef struct {
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/** Offset 0x00DB
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**/
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UINT8 UnusedUpdSpace3[105];
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UINT8 UnusedUpdSpace4[105];
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/** Offset 0x0144 - MMA Test Content Pointer
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Pointer to MMA Test Content in Memory
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@ -351,15 +362,17 @@ typedef struct {
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**/
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UINT32 MmaTestConfigSize;
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/** Offset 0x0154 - Enable CIO2 Controller
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Enable/disable SKYCAM CIO2 Controller.
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$EN_DIS
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/** Offset 0x0154
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**/
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UINT8 Cio2Enable;
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UINT32 FspCarBase;
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/** Offset 0x0155
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/** Offset 0x0158
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**/
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UINT8 ReservedMemoryInitUpd[171];
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UINT32 FspCarSize;
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/** Offset 0x015C
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**/
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UINT8 ReservedMemoryInitUpd[164];
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} MEMORY_INIT_UPD;
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/** UPD data structure for FspSiliconInitApi
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@ -377,7 +390,7 @@ typedef struct {
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/** Offset 0x0209
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**/
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UINT8 UnusedUpdSpace4[7];
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UINT8 UnusedUpdSpace5[7];
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/** Offset 0x0210 - Logo Pointer
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Points to PEI Display Logo Image
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@ -421,9 +434,11 @@ typedef struct {
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**/
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UINT8 IoBufferOwnership;
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/** Offset 0x0220
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/** Offset 0x0220 - Enable CIO2 Controller
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Enable/disable SKYCAM CIO2 Controller.
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$EN_DIS
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**/
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UINT8 UnusedUpdSpace5;
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UINT8 Cio2Enable;
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/** Offset 0x0221 - Enable eMMC Controller
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Enable/disable eMMC Controller.
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@ -585,7 +600,7 @@ typedef struct {
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Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM.
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$EN_DIS
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**/
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UINT8 RtcLock;
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UINT8 LockDownConfigRtcLock;
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/** Offset 0x0281 - Enable SATA
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Enable/disable SATA controller.
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@ -641,7 +656,302 @@ typedef struct {
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/** Offset 0x02EB
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**/
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UINT8 ReservedSiliconInitUpd[271];
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UINT8 UnusedUpdSpace6[1];
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/** Offset 0x02EC - Enable PCIE RP
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Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
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**/
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UINT8 PcieRpEnable[20];
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/** Offset 0x0300 - Enable PCIE RP PMSCI
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Indicate whether the root port power manager SCI is enabled - 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
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**/
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UINT8 PcieRpPmSci[20];
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/** Offset 0x0314 - Enable PCIE RP CLKREQ Support
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Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
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**/
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UINT8 PcieRpClkReqSupport[20];
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/** Offset 0x0328 - Configure CLKREQ Number
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Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.
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**/
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UINT8 PcieRpClkReqNumber[20];
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/** Offset 0x033C - Enable LAN
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Enable/Disable LAN controller.
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$EN_DIS
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**/
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UINT8 EnableLan;
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/** Offset 0x033D - LAN LTR Programming
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Enable/Disable LTR capabilty of PCH internal LAN.
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$EN_DIS
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**/
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UINT8 LanLtrEnable;
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/** Offset 0x033E - SATA eSATASpeedLimit
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When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable.
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$EN_DIS
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**/
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UINT8 eSATASpeedLimit;
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/** Offset 0x033F - SATA RST RAID0
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Enable/Disable RAID0.
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$EN_DIS
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**/
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UINT8 SataRstRaid0;
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/** Offset 0x0340 - SATA RST RAID1
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Enable/Disable RAID1.
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$EN_DIS
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**/
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UINT8 SataRstRaid1;
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/** Offset 0x0341 - SATA RST RAID10
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Enable/Disable RAID10.
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$EN_DIS
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**/
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UINT8 SataRstRaid10;
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/** Offset 0x0342 - SATA RST RAID5
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Enable/Disable RAID5.
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$EN_DIS
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**/
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UINT8 SataRstRaid5;
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/** Offset 0x0343 - Skip Multi-Processor Initialization
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When this is skipped, boot loader must initialize processors before SilicionInit API. 0: Initialize, 1: Skip
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$EN_DIS
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**/
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UINT8 SkipMpInit;
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/** Offset 0x0344 - Enable PCIE RP HotPlug
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Enable/disable PCIE Root Ports HogPlug. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.
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**/
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UINT8 PcieRpHotPlug[20];
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/** Offset 0x0358 - Enable PCIE RP Function Swap
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Enable/disable PCIE RP function swap. 0: disable, 1: enable. It allows BIOS to use root port function number swapping when root port of function 0 is disabled. NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage. Disabling function swap may have adverse impact on power management.
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$EN_DIS
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**/
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UINT8 RpFunctionSwap;
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/** Offset 0x0359 - USB2 Port Over Current Configuration
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Configure over current pin assignment per USB2 ports. Refer to USB_OVERCURRENT_PIN. 0x08 means "skip over current pin". One byte for each port, byte0 for port0, byte1 for port1, and so on.
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**/
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UINT8 Usb2OverCurrentPin[16];
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/** Offset 0x0369 - USB3 Port Over Current Configuration
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Configure over current pin assignment per USB3 ports. Refer to USB_OVERCURRENT_PIN. 0x08 means "skip over current pin". One byte for each port, byte0 for port0, byte1 for port1, and so on.
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**/
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UINT8 Usb3OverCurrentPin[10];
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/** Offset 0x0373
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**/
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UINT8 UnusedUpdSpace7[1];
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/** Offset 0x0374 - Psi1Threshold
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Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT16 Psi1Threshold[5];
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/** Offset 0x037E - Psi2Threshold
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Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT16 Psi2Threshold[5];
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/** Offset 0x0388 - Psi3Threshold
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State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT16 Psi3Threshold[5];
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/** Offset 0x0392 - Psi3Enable
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Power State 3 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT8 Psi3Enable[5];
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/** Offset 0x0397 - Psi4Enable
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Power State 4 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT8 Psi4Enable[5];
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/** Offset 0x039C - ImonSlope
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Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT8 ImonSlope[5];
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/** Offset 0x03A1 - ImonOffset
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Imon offset correction. Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. 0: Auto Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT8 ImonOffset[5];
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/** Offset 0x03A6 - IccMax
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VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT16 IccMax[5];
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/** Offset 0x03B0 - VrVoltageLimit
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VR Voltage Limit. Range is 0-7999mV. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT16 VrVoltageLimit[5];
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/** Offset 0x03BA - VrConfigEnable
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BIOS configuration of VR 0: Disable 1: Enable. Array index maps to VR 0 = System Agent, 1 = IA Core, 2 = Ring, 3 = GT unsliced, 4 = GT sliced
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**/
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UINT8 VrConfigEnable[5];
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/** Offset 0x03BF
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**/
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UINT8 UnusedUpdSpace8;
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/** Offset 0x03C0 - CPU S3 Resume Hob Data
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CPU S3 Resume Hob Data
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**/
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UINT32 CpuS3ResumeHobData;
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/** Offset 0x03C4 - CpuS3ResumeMtrrData
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Pointer CPU S3 Resume MTRR Data
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**/
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UINT32 CpuS3ResumeMtrrData;
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/** Offset 0x03C8 - CpuS3ResumeMtrrDataSize
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Size of S3 resume MTRR data.
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**/
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UINT16 CpuS3ResumeMtrrDataSize;
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/** Offset 0x03CA - Lock Down Config Global Smi
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Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Value 0: Disable, 1: Enable.
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$EN_DIS
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**/
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UINT8 LockDownConfigGlobalSmi;
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/** Offset 0x03CB - Lock Down Config Bios Interface
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Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. Top Swap bit and the General Control and Status Registers Boot BIOS Straps. Value 0: Disable, 1: Enable.
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$EN_DIS
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**/
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UINT8 LockDownConfigBiosInterface;
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/** Offset 0x03CC - Lock Down Config Bios Lock
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When enabled, the BIOS Region can only be modified from SMM after EndOfDxe protocol is installed. Value 0: Disable, 1: Enable.
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$EN_DIS
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**/
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UINT8 LockDownConfigBiosLock;
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/** Offset 0x03CD - Lock Down Config Spi Eiss
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Enable InSMM.STS (EISS) in SPI If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also in order to write to BIOS regions of SPI Flash. If this bit is clear, then the InSMM.STS is a don't care. The BIOS must set the EISS bit while BIOS Guard support is enabled. Value 0: Clear EISS bit, 1: Set EISS bit.
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$EN_DIS
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**/
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UINT8 LockDownConfigSpiEiss;
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/** Offset 0x03CE - Subsystem Vendor ID
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Subsystem Vendor ID of the PCH devices.
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**/
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UINT16 PchConfigSubSystemVendorId;
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/** Offset 0x03D0 - Subsystem ID
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Subsystem ID of the PCH devices.
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**/
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UINT16 PchConfigSubSystemId;
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/** Offset 0x03D2 - Wol Enable Override
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Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. Value 0: Disable, 1: Enable.
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$EN_DIS
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**/
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UINT8 WakeConfigWolEnableOverride;
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/** Offset 0x03D3 - Pcie Wake From DeepSx
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Determine if enable PCIe to wake from deep Sx. Value 0: Disable, 1: Enable.
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$EN_DIS
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**/
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UINT8 WakeConfigPcieWakeFromDeepSx;
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/** Offset 0x03D4 - Power Management DeepSxPolicy
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Deep Sx Policy. Values 0: PchDeepSxPolDisable, 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn, 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn.
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0 : 0x06
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**/
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UINT8 PmConfigDeepSxPol;
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/** Offset 0x03D5 - Power Management SlpS3MinAssert
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SLP_S3 Minimum Assertion Width Policy. Values 0: PchSlpS360us, 1: PchSlpS31ms, 2: PchSlpS350ms, 3: PchSlpS32s.
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0 : 0x03
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**/
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UINT8 PmConfigSlpS3MinAssert;
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/** Offset 0x03D6 - Power Management SlpS4MinAssert
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SLP_S4 Minimum Assertion Width Policy. Values 0: PchSlpS4PchTime, 1: PchSlpS41s, 2: PchSlpS42s, 3: PchSlpS43s, 4: PchSlpS44s.
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0 : 0x04
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**/
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UINT8 PmConfigSlpS4MinAssert;
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/** Offset 0x03D7 - Power Management SlpSusMinAssert
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SLP_SUS Minimum Assertion Width Policy. Values 0: PchSlpSus0ms, 1: PchSlpSus500ms, 2: PchSlpSus1s, 3: PchSlpSus4s.
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0 : 0x03
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**/
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UINT8 PmConfigSlpSusMinAssert;
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/** Offset 0x03D8 - Power Management SlpAMinAssert
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SLP_A Minimum Assertion Width Policy. Values 0: PchSlpA0ms, 1: PchSlpA4s, 2: PchSlpA98ms, 3: PchSlpA2s.
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0 : 0x03
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**/
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UINT8 PmConfigSlpAMinAssert;
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/** Offset 0x03D9 - Power Management Pci Clock Run
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This member describes whether or not the PCI ClockRun feature of PCH should be enabled. Values 0: Disabled, 1: Enabled
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$EN_DIS
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**/
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UINT8 PmConfigPciClockRun;
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/** Offset 0x03DA - Power Management SLP_X Stretching After SUS Well
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SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled
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$EN_DIS
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**/
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UINT8 PmConfigSlpStrchSusUp;
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/** Offset 0x03DB - Power Management Power Button Override Period
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PCH power button override period. Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s.
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0 : 0x05
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**/
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UINT8 PmConfigPwrBtnOverridePeriod;
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/** Offset 0x03DC - Power Management Power Reset Power Cycle Duration
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Reset Power Cycle Duration could be customized in the unit of second. PCH HW default is 4 seconds, and range is 1~4 seconds. Values: 0x0 - 0s, 0x1 - 1s, 0x2 - 2s, 0x3 - 3s, 0x4 - 4s.
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0 : 0x04
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**/
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UINT8 PmConfigPwrCycDur;
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/** Offset 0x03DD - PCH Serial IRQ Configuration
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Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
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$EN_DIS
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**/
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UINT8 SerialIrqConfigSirqEnable;
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/** Offset 0x03DE - PCH Serial IRQ Mode Select
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Serial IRQ Mode Select. Values: 0: PchQuietMode, 1: PchContinuousMode.
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0 : 0x01
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**/
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UINT8 SerialIrqConfigSirqMode;
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||||
|
||||
/** Offset 0x03DF - PCH Serial IRQ Start Frame Pulse Width
|
||||
Start Frame Pulse Width. Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
|
||||
0 : 0x02
|
||||
**/
|
||||
UINT8 SerialIrqConfigStartFramePulse;
|
||||
|
||||
/** Offset 0x03E0 - PSF Unlock
|
||||
The PSF registers will be locked before 3rd party code execution. This policy unlock the PSF space. NOTE: Do not set this policy "PsfUnlock" unless necessary.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PsfUnlock;
|
||||
|
||||
/** Offset 0x03E1 - IO voltage for I2C controllers
|
||||
Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V.
|
||||
**/
|
||||
UINT8 SerialIoI2cVoltage[6];
|
||||
|
||||
/** Offset 0x03E7
|
||||
**/
|
||||
UINT8 ReservedSiliconInitUpd[19];
|
||||
} SILICON_INIT_UPD;
|
||||
|
||||
#define FSP_UPD_SIGNATURE 0x244450554C4B5324 /* '$SKLUPD$' */
|
||||
|
|
@ -694,7 +1004,7 @@ typedef struct {
|
|||
} UPD_DATA_REGION;
|
||||
|
||||
#define FSP_IMAGE_ID 0x245053464C4B5324 /* '$SKLFSP$' */
|
||||
#define FSP_IMAGE_REV 0x01070000
|
||||
#define FSP_IMAGE_REV 0x01080100
|
||||
|
||||
/** VPD data structure
|
||||
**/
|
||||
|
|
|
|||
Loading…
Reference in New Issue