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northbridge/amd/agesa/*: Add whitespace around '<<' 

Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2017-06-27 23:14:51 +02:00 committed by Stefan Reinauer
parent 168ef399c4
commit 27e1801ea7
9 changed files with 59 additions and 59 deletions
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28
src/northbridge/amd/agesa/family10/northbridge.c
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@ -63,14 +63,14 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.mask |= temp<<21; d.mask |= temp << 21;
temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
d.mask |= (temp & 1); // enable bit d.mask |= (temp & 1); // enable bit
d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.base |= temp<<21; d.base |= temp << 21;
return d; return d;
} }
@ -82,12 +82,12 @@ static u32 check_segn(device_t dev, u32 segbusn, u32 nodes,
if ((segbusn & 0xff)>(0xe0-1)) {// use next segn if ((segbusn & 0xff)>(0xe0-1)) {// use next segn
u32 segn = (segbusn >> 8) & 0x0f; u32 segn = (segbusn >> 8) & 0x0f;
segn++; segn++;
segbusn = segn<<8; segbusn = segn << 8;
} }
if (segbusn>>8) { if (segbusn>>8) {
u32 val; u32 val;
val = pci_read_config32(dev, 0x160); val = pci_read_config32(dev, 0x160);
val &= ~(0xf<<25); val &= ~(0xf << 25);
val |= (segbusn & 0xf00)<<(25-8); val |= (segbusn & 0xf00)<<(25-8);
pci_write_config32(dev, 0x160, val); pci_write_config32(dev, 0x160, val);
} }
@ -135,9 +135,9 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
index = (reg-0xc0)>>3; index = (reg-0xc0)>>3;
val = (nodeid & 0x3f); // 6 bits used val = (nodeid & 0x3f); // 6 bits used
sysconf.conf_io_addr[index] = val | ((io_max<<8) & 0xfffff000); //limit : with nodeid sysconf.conf_io_addr[index] = val | ((io_max << 8) & 0xfffff000); //limit : with nodeid
val = 3 | ((linkn & 0x7)<<4); // 8 bits used val = 3 | ((linkn & 0x7)<<4); // 8 bits used
sysconf.conf_io_addrx[index] = val | ((io_min<<8) & 0xfffff000); // base : with enable bit sysconf.conf_io_addrx[index] = val | ((io_min << 8) & 0xfffff000); // base : with enable bit
if (sysconf.io_addr_num<(index+1)) if (sysconf.io_addr_num<(index+1))
sysconf.io_addr_num = index+1; sysconf.io_addr_num = index+1;
@ -166,11 +166,11 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
for (i = 0; i < sysconf.nodes; i++) for (i = 0; i < sysconf.nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for (i = 0; i < sysconf.nodes; i++) for (i = 0; i < sysconf.nodes; i++)
pci_write_config32(__f1_dev[i], reg, tempreg); pci_write_config32(__f1_dev[i], reg, tempreg);
} }
@ -181,7 +181,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
for (i = 0; i < nodes; i++) for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
@ -267,7 +267,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{ {
u32 val; u32 val;
val = 1 | (nodeid<<4) | (linkn<<12); val = 1 | (nodeid << 4) | (linkn << 12);
/* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,
0x3c0:0x3df */ 0x3c0:0x3df */
f1_write_config32(0xf4, val); f1_write_config32(0xf4, val);
@ -329,7 +329,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, unsigned nodeid, unsi
if (!reg) { if (!reg) {
//because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
u32 index = get_io_addr_index(nodeid, link); u32 index = get_io_addr_index(nodeid, link);
reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255
} }
resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
@ -366,7 +366,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link
// but we need one index to differ them. so same node and // but we need one index to differ them. so same node and
// same link can have multi range // same link can have multi range
u32 index = get_mmio_addr_index(nodeid, link); u32 index = get_mmio_addr_index(nodeid, link);
reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63
} }
resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
@ -669,7 +669,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
hole = pci_read_config32(__f1_dev[i], 0xf0); hole = pci_read_config32(__f1_dev[i], 0xf0);
if (hole & 1) { // we find the hole if (hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
mem_hole.node_id = i; // record the node No with hole mem_hole.node_id = i; // record the node No with hole
break; // only one hole break; // only one hole
} }
@ -936,7 +936,7 @@ static void cpu_bus_scan(device_t dev)
nb_cfg_54 = 0; nb_cfg_54 = 0;
ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf); ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
if (ApicIdCoreIdSize) { if (ApicIdCoreIdSize) {
siblings = (1<<ApicIdCoreIdSize)-1; siblings = (1 << ApicIdCoreIdSize)-1;
} else { } else {
siblings = 3; //quad core siblings = 3; //quad core
} }

6
src/northbridge/amd/agesa/family10/reset_test.h
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@ -23,9 +23,9 @@
#define NODE_ID 0x60 #define NODE_ID 0x60
#define HT_INIT_CONTROL 0x6c #define HT_INIT_CONTROL 0x6c
#define HTIC_ColdR_Detect (1<<4) #define HTIC_ColdR_Detect (1 << 4)
#define HTIC_BIOSR_Detect (1<<5) #define HTIC_BIOSR_Detect (1 << 5)
#define HTIC_INIT_Detect (1<<6) #define HTIC_INIT_Detect (1 << 6)
static inline u32 warm_reset_detect(u8 nodeid) static inline u32 warm_reset_detect(u8 nodeid)
{ {

10
src/northbridge/amd/agesa/family12/amdfam12_conf.c
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@ -53,12 +53,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
device_t dev; device_t dev;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
for (i = 0; i < nodes; i++) { for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 1); dev = NODE_PCI(i, 1);
pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
} }
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for (i = 0; i < nodes; i++) { for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 1); dev = NODE_PCI(i, 1);
pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
@ -98,10 +98,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
pci_write_config32(__f1_dev[0], reg+4, tempreg); pci_write_config32(__f1_dev[0], reg+4, tempreg);
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
pci_write_config32(__f1_dev[0], reg, tempreg); pci_write_config32(__f1_dev[0], reg, tempreg);
} }
@ -111,7 +111,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
pci_write_config32(__f1_dev[0], reg+4, tempreg); pci_write_config32(__f1_dev[0], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
pci_write_config32(__f1_dev[0], reg, tempreg); pci_write_config32(__f1_dev[0], reg, tempreg);

8
src/northbridge/amd/agesa/family12/northbridge.c
View File

@ -108,7 +108,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
u32 val; u32 val;
printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
val = 1 | (nodeid<<4) | (linkn<<12); val = 1 | (nodeid << 4) | (linkn << 12);
/* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb,
0x3c0:0x3df */ 0x3c0:0x3df */
f1_write_config32(0xf4, val); f1_write_config32(0xf4, val);
@ -162,7 +162,7 @@ static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsi
if (!reg) { if (!reg) {
//because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
u32 index = get_io_addr_index(nodeid, link); u32 index = get_io_addr_index(nodeid, link);
reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255
} }
resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
@ -198,7 +198,7 @@ static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link
// but we need one index to differ them. so same node and // but we need one index to differ them. so same node and
// same link can have multi range // same link can have multi range
u32 index = get_mmio_addr_index(nodeid, link); u32 index = get_mmio_addr_index(nodeid, link);
reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63
} }
resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
@ -280,7 +280,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
if (d.mask & 1) { if (d.mask & 1) {
hole = pci_read_config32(__f1_dev[0], 0xf0); hole = pci_read_config32(__f1_dev[0], 0xf0);
if (hole & 1) { // we find the hole if (hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
mem_hole.node_id = 0; // record the node No with hole mem_hole.node_id = 0; // record the node No with hole
} }
} }

10
src/northbridge/amd/agesa/family14/amdfam14_conf.c
View File

@ -53,12 +53,12 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
device_t dev; device_t dev;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
for (i = 0; i < nodes; i++) { for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 1); dev = NODE_PCI(i, 1);
pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg); pci_write_config32(dev, 0xC4 + ht_c_index * 8, tempreg);
} }
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for (i = 0; i < nodes; i++) { for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 1); dev = NODE_PCI(i, 1);
pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg);
@ -98,10 +98,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
pci_write_config32(__f1_dev[0], reg+4, tempreg); pci_write_config32(__f1_dev[0], reg+4, tempreg);
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
pci_write_config32(__f1_dev[0], reg, tempreg); pci_write_config32(__f1_dev[0], reg, tempreg);
} }
@ -111,7 +111,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
pci_write_config32(__f1_dev[0], reg+4, tempreg); pci_write_config32(__f1_dev[0], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
pci_write_config32(__f1_dev[0], reg, tempreg); pci_write_config32(__f1_dev[0], reg, tempreg);

14
src/northbridge/amd/agesa/family15/northbridge.c
View File

@ -67,12 +67,12 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.mask |= temp<<21; d.mask |= temp << 21;
temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
d.mask |= (temp & 1); // enable bit d.mask |= (temp & 1); // enable bit
d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.base |= temp<<21; d.base |= temp << 21;
return d; return d;
} }
@ -82,10 +82,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 i; u32 i;
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
for (i = 0; i < node_nums; i++) for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for (i = 0; i < node_nums; i++) for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg); pci_write_config32(__f1_dev[i], reg, tempreg);
} }
@ -95,7 +95,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 i; u32 i;
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
for (i = 0; i < nodes; i++) for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
@ -174,7 +174,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{ {
u32 val; u32 val;
val = 1 | (nodeid<<4) | (linkn<<12); val = 1 | (nodeid << 4) | (linkn << 12);
/* it will routing /* it will routing
* (1)mmio 0xa0000:0xbffff * (1)mmio 0xa0000:0xbffff
* (2)io 0x3b0:0x3bb, 0x3c0:0x3df * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
@ -668,7 +668,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
if (!(d.mask & 1)) continue; // no memory on this node if (!(d.mask & 1)) continue; // no memory on this node
hole = pci_read_config32(__f1_dev[i], 0xf0); hole = pci_read_config32(__f1_dev[i], 0xf0);
if (hole & 1) { // we find the hole if (hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
mem_hole.node_id = i; // record the node No with hole mem_hole.node_id = i; // record the node No with hole
break; // only one hole break; // only one hole
} }

14
src/northbridge/amd/agesa/family15rl/northbridge.c
View File

@ -66,12 +66,12 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.mask |= temp<<21; d.mask |= temp << 21;
temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
d.mask |= (temp & 1); // enable bit d.mask |= (temp & 1); // enable bit
d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.base |= temp<<21; d.base |= temp << 21;
return d; return d;
} }
@ -81,10 +81,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 i; u32 i;
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
for (i = 0; i < node_nums; i++) for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for (i = 0; i < node_nums; i++) for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg); pci_write_config32(__f1_dev[i], reg, tempreg);
} }
@ -94,7 +94,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 i; u32 i;
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
for (i = 0; i < nodes; i++) for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
@ -173,7 +173,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{ {
u32 val; u32 val;
val = 1 | (nodeid<<4) | (linkn<<12); val = 1 | (nodeid << 4) | (linkn << 12);
/* it will routing /* it will routing
* (1)mmio 0xa0000:0xbffff * (1)mmio 0xa0000:0xbffff
* (2)io 0x3b0:0x3bb, 0x3c0:0x3df * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
@ -664,7 +664,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
if (!(d.mask & 1)) continue; // no memory on this node if (!(d.mask & 1)) continue; // no memory on this node
hole = pci_read_config32(__f1_dev[i], 0xf0); hole = pci_read_config32(__f1_dev[i], 0xf0);
if (hole & 1) { // we find the hole if (hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
mem_hole.node_id = i; // record the node No with hole mem_hole.node_id = i; // record the node No with hole
break; // only one hole break; // only one hole
} }

14
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -65,12 +65,12 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.mask |= temp<<21; d.mask |= temp << 21;
temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
d.mask |= (temp & 1); // enable bit d.mask |= (temp & 1); // enable bit
d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.base |= temp<<21; d.base |= temp << 21;
return d; return d;
} }
@ -80,10 +80,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 i; u32 i;
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
for (i = 0; i < node_nums; i++) for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for (i = 0; i < node_nums; i++) for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg); pci_write_config32(__f1_dev[i], reg, tempreg);
} }
@ -93,7 +93,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 i; u32 i;
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
for (i = 0; i < nodes; i++) for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
@ -172,7 +172,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{ {
u32 val; u32 val;
val = 1 | (nodeid<<4) | (linkn<<12); val = 1 | (nodeid << 4) | (linkn << 12);
/* it will routing /* it will routing
* (1)mmio 0xa0000:0xbffff * (1)mmio 0xa0000:0xbffff
* (2)io 0x3b0:0x3bb, 0x3c0:0x3df * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
@ -663,7 +663,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
if (!(d.mask & 1)) continue; // no memory on this node if (!(d.mask & 1)) continue; // no memory on this node
hole = pci_read_config32(__f1_dev[i], 0xf0); hole = pci_read_config32(__f1_dev[i], 0xf0);
if (hole & 1) { // we find the hole if (hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
mem_hole.node_id = i; // record the node No with hole mem_hole.node_id = i; // record the node No with hole
break; // only one hole break; // only one hole
} }

14
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -65,12 +65,12 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too
temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.mask |= temp<<21; d.mask |= temp << 21;
temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
d.mask |= (temp & 1); // enable bit d.mask |= (temp & 1); // enable bit
d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
d.base |= temp<<21; d.base |= temp << 21;
return d; return d;
} }
@ -80,10 +80,10 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 i; u32 i;
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn << 4) | ((io_max&0xf0)<<(12-4)); //limit
for (i = 0; i < node_nums; i++) for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? tempreg = 3 /*| (3 << 4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for (i = 0; i < node_nums; i++) for (i = 0; i < node_nums; i++)
pci_write_config32(__f1_dev[i], reg, tempreg); pci_write_config32(__f1_dev[i], reg, tempreg);
} }
@ -93,7 +93,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
u32 i; u32 i;
u32 tempreg; u32 tempreg;
/* io range allocation */ /* io range allocation */
tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit tempreg = (nodeid&0xf) | (linkn << 4) | (mmio_max&0xffffff00); //limit
for (i = 0; i < nodes; i++) for (i = 0; i < nodes; i++)
pci_write_config32(__f1_dev[i], reg+4, tempreg); pci_write_config32(__f1_dev[i], reg+4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
@ -172,7 +172,7 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{ {
u32 val; u32 val;
val = 1 | (nodeid<<4) | (linkn<<12); val = 1 | (nodeid << 4) | (linkn << 12);
/* it will routing /* it will routing
* (1)mmio 0xa0000:0xbffff * (1)mmio 0xa0000:0xbffff
* (2)io 0x3b0:0x3bb, 0x3c0:0x3df * (2)io 0x3b0:0x3bb, 0x3c0:0x3df
@ -678,7 +678,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
if (!(d.mask & 1)) continue; // no memory on this node if (!(d.mask & 1)) continue; // no memory on this node
hole = pci_read_config32(__f1_dev[i], 0xf0); hole = pci_read_config32(__f1_dev[i], 0xf0);
if (hole & 2) { // we find the hole if (hole & 2) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
mem_hole.node_id = i; // record the node No with hole mem_hole.node_id = i; // record the node No with hole
break; // only one hole break; // only one hole
} }