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AMD Steppe Eagle: Add northbridge files for new SoC family 

Add the northbridge file for AMD's new Mullins and Steppe Eagle
processor family.  Since the processor family name is not the
same across AMD's sales and marketing channels, I have elected
to use part of the processor ID as the family name.  The intent
is to reduce confusion since the processor ID is the same for
both families.  This northbridge support has only been validated
on the AMD Embedded variants ("Steppe Eagle").

The AGESA wrappers in coreboot have a function that is intended to
mirror the UMA memory allocation performed during memory initialization
by AGESA.  Update the Steppe Eagle memory allocation to mimic the
memory reservation done inside the AGESA BLOB.

Change the default CBMEM address, the default video BIOS device ID,
and a couple of other defaults to match changes in coreboot community
code.

The northbridge chip.h specifies how many processor sockets, how
many channels, and how many DIMM slots are supported by the
northbridge.  Steppe Eagle does not permit multisocket systems
and has only one memory controller channel.

Change-Id: I20d8b78e3b153cda2dd05100fbb75e2ebadd9e08
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/6678
Tested-by: build bot (Jenkins)
Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
This commit is contained in:
Bruce Griffith 2014-08-15 11:46:25 -06:00
parent 1a59039c24
commit 27ed80bce1
17 changed files with 1794 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
src/northbridge/amd/agesa/00730F01/Kconfig Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
## Copyright (C) 2014 Sage Electronic Engineering, LLC
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config NORTHBRIDGE_AMD_AGESA_00730F01
bool
select MMCONF_SUPPORT
if NORTHBRIDGE_AMD_AGESA_00730F01
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config HW_MEM_HOLE_SIZE_AUTO_INC
bool
default n
config MMCONF_BASE_ADDRESS
hex
default 0xF8000000
config MMCONF_BUS_NUMBER
int
default 64
config VGA_BIOS_ID
string
default "1002,9850"
help
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
config VGA_BIOS_FILE
string
default "3rdparty/northbridge/amd/00730F01/VBIOS.bin"
endif

25
src/northbridge/amd/agesa/00730F01/Makefile.inc Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
romstage-y += callouts_for_00730F01.c
romstage-y += dimmSpd.c
ramstage-y += northbridge.c
ramstage-y += callouts_for_00730F01.c
ramstage-y += dimmSpd.c

100
src/northbridge/amd/agesa/00730F01/acpi/northbridge.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Note: Only need HID on Primary Bus */
External (TOM1)
External (TOM2)
Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
/* Describe the Northbridge devices */
Method(_BBN, 0, NotSerialized) /* Bus number = 0 */
{
Return(Zero)
}
Method(_STA, 0, NotSerialized)
{
Return(0x0B) /* Status is visible */
}
Method(_PRT,0, NotSerialized)
{
If(PMOD)
{
Return(APR0) /* APIC mode */
}
Return (PR0) /* PIC Mode */
}
Device(AMRT) {
Name(_ADR, 0x00000000)
} /* end AMRT */
/* Gpp 0 */
Device(PBR4) {
Name(_ADR, 0x00020001)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS4) } /* APIC mode */
Return (PS4) /* PIC Mode */
} /* end _PRT */
} /* end PBR4 */
/* Gpp 1 */
Device(PBR5) {
Name(_ADR, 0x00020002)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS5) } /* APIC mode */
Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
/* Gpp 2 */
Device(PBR6) {
Name(_ADR, 0x00020003)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS6) } /* APIC mode */
Return (PS6) /* PIC Mode */
} /* end _PRT */
} /* end PBR6 */
/* Gpp 3 */
Device(PBR7) {
Name(_ADR, 0x00020004)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS7) } /* APIC mode */
Return (PS7) /* PIC Mode */
} /* end _PRT */
} /* end PBR7 */
/* Gpp 4 */
Device(PBR8) {
Name(_ADR, 0x00020005)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PMOD){ Return(APS8) } /* APIC mode */
Return (PS8) /* PIC Mode */
} /* end _PRT */
} /* end PBR8 */

37
src/northbridge/amd/agesa/00730F01/callouts_for_00730F01.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "agesawrapper.h"
#include "amdlib.h"
#include "Ids.h"
#include "OptionsIds.h"
#include "heapManager.h"
#include "FchPlatform.h"
#include "cbfs.h"
#include "dimmSpd.h"
#include "callouts_for_00730F01.h"
#include "northbridge/amd/agesa/def_callouts.h"
AGESA_STATUS ReadSpd_00730F01 (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
return Status;
}

28
src/northbridge/amd/agesa/00730F01/callouts_for_00730F01.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef CALLOUTS_AMD_AGESA_FAM16_0X30_H
#define CALLOUTS_AMD_AGESA_FAM16_0X30_H
#include "Porting.h"
#include "AGESA.h"
AGESA_STATUS ReadSpd_00730F01 (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
#endif /* CALLOUTS_AMD_AGESA_FAM16_0X30_H */

28
src/northbridge/amd/agesa/00730F01/chip.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _AGESA_00730F01_CHIP_H_
#define _AGESA_00730F01_CHIP_H_
struct northbridge_amd_agesa_00730F01_config
{
u8 spdAddrLookup[1][1][2];
};
#endif /* _AGESA_00730F01_CHIP_H_ */

173
src/northbridge/amd/agesa/00730F01/dimmSpd.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/pci_def.h>
#include <device/device.h>
/* warning: Porting.h includes an open #pragma pack(1) */
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include "dimmSpd.h"
#include "chip.h"
#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
/*-----------------------------------------------------------------------------
*
* readSmbusByteData - read a single SPD byte from any offset
*/
static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
{
unsigned int status;
UINT64 limit;
address |= 1; // set read bit
__outbyte (iobase + 0, 0xFF); // clear error status
__outbyte (iobase + 1, 0x1F); // clear error status
__outbyte (iobase + 3, offset); // offset in eeprom
__outbyte (iobase + 4, address); // slave address and read bit
__outbyte (iobase + 2, 0x48); // read byte command
// time limit to avoid hanging for unexpected error status (should never happen)
limit = __rdtsc () + 2000000000 / 10;
for (;;)
{
status = __inbyte (iobase);
if (__rdtsc () > limit) break;
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
buffer [0] = __inbyte (iobase + 5);
if (status == 2) status = 0; // check for done with no errors
return status;
}
/*-----------------------------------------------------------------------------
*
* readSmbusByte - read a single SPD byte from the default offset
* this function is faster function readSmbusByteData
*/
static int readSmbusByte (int iobase, int address, char *buffer)
{
unsigned int status;
UINT64 limit;
__outbyte (iobase + 0, 0xFF); // clear error status
__outbyte (iobase + 2, 0x44); // read command
// time limit to avoid hanging for unexpected error status
limit = __rdtsc () + 2000000000 / 10;
for (;;)
{
status = __inbyte (iobase);
if (__rdtsc () > limit) break;
if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
if ((status & 1) == 1) continue; // HostBusy set, keep waiting
break;
}
buffer [0] = __inbyte (iobase + 5);
if (status == 2) status = 0; // check for done with no errors
return status;
}
/*---------------------------------------------------------------------------
*
* readspd - Read one or more SPD bytes from a DIMM.
* Start with offset zero and read sequentially.
* Optimization relies on autoincrement to avoid
* sending offset for every byte.
* Reads 128 bytes in 7-8 ms at 400 KHz.
*/
static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
{
int index, error;
printk(BIOS_SPEW, "-------------READING SPD-----------\n");
printk(BIOS_SPEW, "iobase: 0x%08X, SmbusSlave: 0x%08X, count: %d\n",
iobase, SmbusSlaveAddress, count);
/* read the first byte using offset zero */
error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
if (error) {
printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
return error;
}
/* read the remaining bytes using auto-increment for speed */
for (index = 1; index < count; index++)
{
error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
if (error) {
printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
return error;
}
}
printk(BIOS_SPEW, "\n");
printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n");
return 0;
}
static void writePmReg (int reg, int data)
{
__outbyte (0xCD6, reg);
__outbyte (0xCD7, data);
}
static void setupFch (int ioBase)
{
writePmReg (0x2D, ioBase >> 8);
writePmReg (0x2C, ioBase | 1);
__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
}
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
{
int spdAddress, ioBase;
ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
ROMSTAGE_CONST struct northbridge_amd_agesa_00730F01_config *config = dev->chip_info;
if ((dev == 0) || (config == 0))
return AGESA_ERROR;
if (info->SocketId >= DIMENSION(config->spdAddrLookup ))
return AGESA_ERROR;
if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] ))
return AGESA_ERROR;
if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0]))
return AGESA_ERROR;
spdAddress = config->spdAddrLookup
[info->SocketId] [info->MemChannelId] [info->DimmId];
if (spdAddress == 0) return AGESA_ERROR;
ioBase = 0xB00;
setupFch (ioBase);
return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
}

26
src/northbridge/amd/agesa/00730F01/dimmSpd.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _DIMMSPD_H_
#define _DIMMSPD_H_
AGESA_STATUS
AmdMemoryReadSPD (IN UINT32 Func, IN UINT32 Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData);
#endif

1154
src/northbridge/amd/agesa/00730F01/northbridge.c Normal file
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26
src/northbridge/amd/agesa/00730F01/northbridge.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H
#define NORTHBRIDGE_AMD_AGESA_FAM16H_H
static struct device_operations pci_domain_ops;
static struct device_operations cpu_bus_ops;
#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */

1
src/northbridge/amd/agesa/Kconfig
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@ -37,5 +37,6 @@ source src/northbridge/amd/agesa/family14/Kconfig
source src/northbridge/amd/agesa/family15/Kconfig
source src/northbridge/amd/agesa/family15tn/Kconfig
source src/northbridge/amd/agesa/family16kb/Kconfig
source src/northbridge/amd/agesa/00730F01/Kconfig
endif # NORTHBRIDGE_AMD_AGESA

1
src/northbridge/amd/agesa/Makefile.inc
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@ -22,6 +22,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01) += 00730F01
romstage-y += def_callouts.c
ramstage-y += def_callouts.c

23
src/northbridge/amd/agesa/common/Makefile.inc Normal file
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#
# This file is part of the coreboot project.
#
# Copyright (C) 2014 Sage Electronic Engineering, LLC
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
romstage-y += ../../../../device/dram/ddr3.c
romstage-y += common.c
ramstage-y += common.c

83
src/northbridge/amd/agesa/common/common.c Normal file
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@ -0,0 +1,83 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "AGESA.h"
#include "common.h"
#include <device/dram/ddr3.h>
#include <string.h>
#include <cbfs.h>
AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
#ifdef __PRE_RAM__
AGESA_READ_SPD_PARAMS *info = ConfigPtr;
size_t spd_file_length;
if (info->MemChannelId > CONFIG_AGESA_DDR3_CHANNEL_MAX)
return AGESA_ERROR;
if (info->SocketId != 0)
return AGESA_ERROR;
if (info->DimmId != 0)
return AGESA_ERROR;
char *spd_file;
spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", CBFS_TYPE_SPD_BIN, &spd_file_length);
if (!spd_file)
die("file [spd.bin] not found in CBFS");
printk(BIOS_DEBUG, "\nCBFS SPD file length = 0x%x bytes\n", (unsigned int)spd_file_length);
if (CONFIG_MULTIPLE_DDR_SPD) {
struct multi_spd_info *spd_info = (struct multi_spd_info *)info->Buffer;
printk(BIOS_DEBUG, "Multiple DDR SPD: using offset %d\n", spd_info->offset);
if (spd_info->offset > (spd_file_length / spd_info->size))
printk(BIOS_EMERG, "Multiple SPD offset is greater than SPD length\n");
else {
spd_file += spd_info->offset * spd_info->size;
spd_file_length = spd_info->size;
}
}
memcpy((char*)info->Buffer, spd_file, spd_file_length);
u16 crc = spd_ddr3_calc_crc(info->Buffer, spd_file_length);
if (crc == 0){
printk(BIOS_EMERG, "Error: Unable to calculate CRC on SPD\n");
return AGESA_UNSUPPORTED;
}
if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0))
|| (info->Buffer[SPD_CRC_LO] != (crc & 0xff))
|| (info->Buffer[SPD_CRC_HI] != (crc >> 8))) {
printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n");
info->Buffer[SPD_CRC_LO] = crc & 0xff;
info->Buffer[SPD_CRC_HI] = crc >> 8;
u16 i;
printk(BIOS_SPEW, "\nDisplay the SPD");
for (i = 0; i < spd_file_length; i++) {
if((i % 16) == 0x00)
printk(BIOS_SPEW, "\n%02x: ",i);
printk(BIOS_SPEW, "%02x ", info->Buffer[i]);
}
printk(BIOS_SPEW, "\n");
}
return AGESA_SUCCESS;
#else
return AGESA_UNSUPPORTED;
#endif
}

34
src/northbridge/amd/agesa/common/common.h Normal file
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@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _AGESA_COMMON_H_
#define _AGESA_COMMON_H_
#define SPD_CRC_HI 127
#define SPD_CRC_LO 126
struct multi_spd_info {
u8 offset; // defines spd 0,1,...
u8 size; // defines spd size
};
AGESA_STATUS
common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
#endif

2
src/northbridge/amd/agesa/def_callouts.c
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@ -103,7 +103,7 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
return Status;
}
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB || CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01
/* FIXME: we would like GFX disable for fam14 too for headless systems. */
AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt)
{

2
src/northbridge/amd/agesa/def_callouts.h
View File

@ -24,7 +24,7 @@
#include "Porting.h"
#include "AGESA.h"
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB
#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB || CONFIG_NORTHBRIDGE_AMD_AGESA_00730F01
#define BIOS_HEAP_START_ADDRESS 0x010000000
#define BIOS_HEAP_SIZE 0x30000