GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

x4x: add non documented vram sizes 

The Intel documtentation, "Intel ® 4 Series Chipset Family"
mentions the possibility of 1, 4, 8 and 16M of preallocated
memory for the IGD, but does not document this.

This allows to set those undocumented values.
TESTED on ga-g41m-es2l with 2G dimm in one slot and 2x2G.

Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15491
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Arthur Heymans 2016-06-18 21:08:58 +02:00 committed by Patrick Georgi
parent 5c4748b342
commit 27f94eea6c
2 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/x4x/ram_calc.c
View File

@ -28,7 +28,7 @@
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
{
static const u16 ggc2uma[] = { 0, 0, 0, 0, 0,
static const u16 ggc2uma[] = { 0, 1, 4, 8, 16,
32, 48, 64, 128, 256, 96, 160, 224, 352 };
if (gms > ARRAY_SIZE(ggc2uma))

3
src/northbridge/intel/x4x/raminit_ddr2.c
View File

@ -1625,7 +1625,8 @@ static void mmap_ddr2(struct sysinfo *s)
u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud;
u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit;
u16 ggc;
u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 };
u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96,
160, 224, 352 };
u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4};
ggc = pci_read_config16(PCI_DEV(0,0,0), 0x52);