From 27fdfc60bc3b5ab1c2e59599d54093bbb25d37a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Thu, 7 Apr 2022 15:03:09 +0200 Subject: [PATCH] soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and CLKREQ signals. ADL-S CPUs do not have Thunderbolt. Based on the Intel DOC #619501 and #619362. Signed-off-by: Michał Żygowski Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Reviewed-by: Subrata Banik --- src/soc/intel/alderlake/Kconfig | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 4ab58d4ea7..1507d6f235 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -212,16 +212,17 @@ config MAX_PCH_ROOT_PORTS default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 if SOC_INTEL_ALDERLAKE_PCH_N default 12 if SOC_INTEL_ALDERLAKE_PCH_P + default 28 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_CPU_ROOT_PORTS int default 1 if SOC_INTEL_ALDERLAKE_PCH_M default 0 if SOC_INTEL_ALDERLAKE_PCH_N - default 3 if SOC_INTEL_ALDERLAKE_PCH_P + default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S config MAX_TBT_ROOT_PORTS int - default 0 if SOC_INTEL_ALDERLAKE_PCH_N + default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S default 2 if SOC_INTEL_ALDERLAKE_PCH_M default 4 if SOC_INTEL_ALDERLAKE_PCH_P @@ -234,12 +235,14 @@ config MAX_PCIE_CLOCK_SRC default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 7 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_PCIE_CLOCK_REQ int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 10 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S config SMM_TSEG_SIZE hex