mb/google/kahlee/treeya: Update the memory timing table for Treeya to the 2T table

Rename the table from Liara specific to simply specifying
that it's using 2T command rate

BUG=139841929
TEST=build and do stress test

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Peichao Wang 2019-08-27 16:51:04 +08:00 committed by Martin Roth
parent 4510a8f4b3
commit 28086f0d2c
1 changed files with 3 additions and 3 deletions

View File

@ -39,7 +39,7 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
PSO_END PSO_END
}; };
/* Liara-specific 2T memory configuration */ /* Liara-specific 2T memory configuration */
static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { static const PSO_ENTRY DDR4_2T_MemoryConfiguration[] = {
DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH),
@ -58,9 +58,9 @@ static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
void OemPostParams(AMD_POST_PARAMS *PostParams) void OemPostParams(AMD_POST_PARAMS *PostParams)
{ {
if (CONFIG(BOARD_GOOGLE_LIARA)) if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA))
PostParams->MemConfig.PlatformMemoryConfiguration = PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4LiaraMemoryConfiguration; (PSO_ENTRY *)DDR4_2T_MemoryConfiguration;
else else
PostParams->MemConfig.PlatformMemoryConfiguration = PostParams->MemConfig.PlatformMemoryConfiguration =
(PSO_ENTRY *)DDR4PlatformMemoryConfiguration; (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;