GOOGLE/SNOW: get graphics working
This adds support for display bring-up on Snow. It includes framebuffer initialization and LCD enable functions. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/3116 Tested-by: build bot (Jenkins)
This commit is contained in:
Ronald G. Minnich
parent
2c88cc0696
commit
2810afa57d
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@ -27,6 +27,7 @@
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#include <arch/io.h>
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#include <stdlib.h>
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#include <string.h>
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#include <time.h>
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#include <console/console.h>
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#include <cpu/samsung/exynos5250/cpu.h>
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#include <cpu/samsung/exynos5250/power.h>
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@ -41,6 +42,28 @@
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#include "cpu/samsung/exynos5250/s5p-dp.h"
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#include "s5p-dp-core.h"
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/*
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* Here is the rough outline of how we bring up the display:
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* 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
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* 2. Source determines video mode by reading DPCD receiver capability field
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* (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
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* 0000Dh).
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* 3. Sink replies DPCD receiver capability field.
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* 4. Source starts EDID read thru I2C-over-AUX.
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* 5. Sink replies EDID thru I2C-over-AUX.
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* 6. Source determines link configuration, such as MAX_LINK_RATE and
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* MAX_LANE_COUNT. Source also determines which type of eDP Authentication
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* method to use and writes DPCD link configuration field (DPCD 00100h to
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* 0010Ah) including eDP configuration set (DPCD 0010Ah).
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* 7. Source starts link training. Sink does clock recovery and equalization.
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* 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
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* 9. Sink replies DPCD link status field. If main link is not stable, Source
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* repeats Step 7.
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* 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
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* parameters and recovers stream clock.
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* 11. Source sends video data.
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*/
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/* To help debug any init errors here, define a list of possible errors */
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enum {
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ERR_PLL_NOT_UNLOCKED = 2,
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@ -126,10 +149,8 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase,
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{
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unsigned int val;
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u32 fbsize;
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struct exynos5_fimd *fimd =
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samsung_get_base_fimd();
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struct exynos5_disp_ctrl *disp_ctrl =
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samsung_get_base_disp_ctrl();
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struct exynos5_fimd *fimd = samsung_get_base_fimd();
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struct exynos5_disp_ctrl *disp_ctrl = samsung_get_base_disp_ctrl();
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writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1);
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val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET);
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@ -191,7 +212,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
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struct video_info *video_info)
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{
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int timeout = 0;
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u32 start;
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u32 start, end;
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struct exynos5_dp *base = dp->base;
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s5p_dp_config_video_slave_mode(dp, video_info);
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@ -206,16 +227,18 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp,
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return -ERR_PLL_NOT_UNLOCKED;
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}
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start = get_timer(0);
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start = timer_us();
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end = start + STREAM_ON_TIMEOUT*1000;
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do {
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if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) {
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timeout++;
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break;
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}
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} while (get_timer(start) <= STREAM_ON_TIMEOUT);
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} while (timer_us() < end);
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if (!timeout) {
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printk(BIOS_DEBUG, "Video Clock Not ok\n");
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printk(BIOS_ERR, "Video Clock Not ok after %uus.\n",
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timer_us() - start);
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return -ERR_VIDEO_CLOCK_BAD;
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}
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@ -255,7 +278,6 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp)
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printk(BIOS_DEBUG, "DPCD read error\n");
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return -ERR_DPCD_READ_ERROR1;
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}
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if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
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DPCD_ENHANCED_FRAME_EN |
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(data & DPCD_LANE_COUNT_SET_MASK))) {
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@ -408,6 +430,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
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unsigned int max_lane,
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unsigned int max_rate)
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{
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int pll_is_locked = 0;
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u32 data;
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u32 start;
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int lane;
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@ -417,14 +440,15 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
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clrbits_le32(&base->video_ctl_1, VIDEO_EN);
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start = get_timer(0);
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while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
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while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) {
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if (get_timer(start) > PLL_LOCK_TIMEOUT) {
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/* Ignore this error, and try to continue */
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printk(BIOS_ERR, "PLL is not locked yet.\n");
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break;
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}
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}
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printk(BIOS_SPEW, "PLL is %slocked\n",
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pll_is_locked == PLL_LOCKED ? "": "not ");
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/* Reset Macro */
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setbits_le32(&base->dp_phy_test, MACRO_RST);
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@ -448,6 +472,9 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
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s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
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s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
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printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__,
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dp->link_train.link_rate, dp->link_train.lane_count);
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if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
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(dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
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printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n",
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@ -480,13 +507,14 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
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/* Start HW link training */
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writel(HW_TRAINING_EN, &base->dp_hw_link_training);
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/* Wait unitl HW link training done */
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/* Wait until HW link training done */
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s5p_dp_wait_hw_link_training_done(dp);
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/* Get hardware link training status */
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data = readl(&base->dp_hw_link_training);
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printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data);
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if (data != 0) {
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printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data);
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printk(BIOS_ERR, " H/W link training failure: 0x%x\n", data);
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return -ERR_LINK_TRAINING_FAILURE;
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}
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@ -497,6 +525,8 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp,
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data = readl(&base->lane_count_set);
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dp->link_train.lane_count = data;
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printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n",
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dp->link_train.link_rate, data);
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return 0;
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}
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@ -510,24 +540,19 @@ int dp_controller_init(struct s5p_dp_device *dp_device)
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struct s5p_dp_device *dp = dp_device;
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struct exynos5_dp *base;
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//dp->base = (struct exynos5_dp *)addr;
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/* yes. we're a snow. Yet somehow our config is from a development kit?
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* This Must Change */
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//dp->video_info = &smdk5250_dp_config;
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clock_init_dp_clock();
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power_enable_dp_phy();
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ret = s5p_dp_init_dp(dp);
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if (ret) {
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printk(BIOS_DEBUG, "%s: Could not initialize dp\n", __func__);
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printk(BIOS_ERR, "%s: Could not initialize dp\n", __func__);
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return ret;
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}
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ret = s5p_dp_hw_link_training(dp, dp->video_info->lane_count,
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dp->video_info->link_rate);
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if (ret) {
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printk(BIOS_DEBUG, "unable to do link train\n");
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printk(BIOS_ERR, "unable to do link train\n");
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return ret;
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}
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/* Minimum delay after H/w Link training */
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@ -535,13 +560,13 @@ int dp_controller_init(struct s5p_dp_device *dp_device)
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ret = s5p_dp_enable_scramble(dp);
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if (ret) {
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printk(BIOS_DEBUG, "unable to set scramble mode\n");
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printk(BIOS_ERR, "unable to set scramble mode\n");
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return ret;
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}
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ret = s5p_dp_enable_rx_to_enhanced_mode(dp);
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if (ret) {
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printk(BIOS_DEBUG, "unable to set enhanced mode\n");
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printk(BIOS_ERR, "unable to set enhanced mode\n");
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return ret;
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}
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@ -556,7 +581,7 @@ int dp_controller_init(struct s5p_dp_device *dp_device)
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s5p_dp_init_video(dp);
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ret = s5p_dp_config_video(dp, dp->video_info);
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if (ret) {
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printk(BIOS_DEBUG, "unable to config video\n");
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printk(BIOS_ERR, "unable to config video\n");
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return ret;
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}
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@ -576,10 +601,5 @@ int lcd_ctrl_init(vidinfo_t *panel_info,
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fimd_bypass();
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fb_init(panel_info, lcdbase, panel_data);
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printk(BIOS_SPEW,
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"fb_init(%p, %p, %p) done\n", panel_info, lcdbase, panel_data);
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/* Enable flushing after LCD writes if requested */
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// forget it. lcd_set_flush_dcache(1);
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return ret;
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}
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@ -129,7 +129,8 @@ int s5p_dp_init_analog_func(struct s5p_dp_device *dp)
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start = get_timer(0);
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while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
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if (get_timer(start) > PLL_LOCK_TIMEOUT) {
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printk(BIOS_DEBUG, "%s: PLL is not locked yet\n", __func__);
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printk(BIOS_ERR, "%s: PLL is not locked\n",
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__func__);
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return -1;
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}
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}
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@ -176,9 +177,6 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
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/* Enable AUX CH operation */
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setbits_le32(&base->aux_ch_ctl_2, AUX_EN);
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printk(BIOS_DEBUG, "%s: base: 0x%p, &base->aux_ch_ctl_2: 0x%p, aux_ch_ctl_2: 0x%08x\n",
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__func__, base, &base->aux_ch_ctl_2, readl(&base->aux_ch_ctl_2));
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/* Is AUX CH command reply received? */
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reg = readl(&base->dp_int_sta);
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while (!(reg & RPLY_RECEIV))
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@ -189,8 +187,9 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
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/* Clear interrupt source for AUX CH access error */
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reg = readl(&base->dp_int_sta);
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printk(BIOS_DEBUG, "%s: dp_int_sta: 0x%02x\n", __func__, reg);
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if (reg & AUX_ERR) {
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printk(BIOS_ERR, "%s: AUX_ERR encountered, dp_int_sta: "
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"0x%02x\n", __func__, reg);
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writel(AUX_ERR, &base->dp_int_sta);
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return -1;
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}
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@ -198,7 +197,7 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp)
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/* Check AUX CH error access status */
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reg = readl(&base->dp_int_sta);
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if ((reg & AUX_STATUS_MASK) != 0) {
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printk(BIOS_DEBUG, "AUX CH error happens: %d\n\n",
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printk(BIOS_ERR, "AUX CH error happens: %d\n\n",
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reg & AUX_STATUS_MASK);
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return -1;
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}
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@ -5,6 +5,7 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <cbmem.h>
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#include <arch/cache.h>
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#include <cpu/samsung/exynos5250/fimd.h>
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#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
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#include "chip.h"
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@ -32,7 +33,6 @@ static void exynos_displayport_init(device_t dev)
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unsigned long int fb_size;
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u32 lcdbase;
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printk(BIOS_SPEW, "%s: dev 0x%p, conf 0x%p\n", __func__, dev, conf);
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memset(&vi, 0, sizeof(vi));
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memset(&panel, 0, sizeof(panel));
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@ -61,16 +61,35 @@ static void exynos_displayport_init(device_t dev)
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* The size is a magic number from hardware. Allocate enough for the
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* frame buffer and color map.
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*/
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fb_size = conf->xres * conf->yres * sizeof(unsigned long);
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fb_size = conf->xres * conf->yres * (conf->bpp / 8);
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lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size + 64*KiB);
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printk(BIOS_SPEW, "lcd colormap base is %p\n", (void *)(lcdbase));
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mmio_resource(dev, 0, lcdbase/KiB, 64);
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vi.cmap = (void *)lcdbase;
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/*
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* We need to clean and invalidate the framebuffer region and disable
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* caching as well. We assume that our dcache <--> memory address
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* space is identity-mapped in 1MB chunks, so align accordingly.
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*
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* Note: We may want to do something clever to ensure the framebuffer
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* region is aligned such that we don't change dcache policy for other
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* stuff inadvertantly.
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*
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* FIXME: Is disabling/re-enabling the MMU entirely necessary?
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*/
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uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
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uint32_t upper = ALIGN_UP(lcdbase + fb_size + 64*KiB, MiB);
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dcache_clean_invalidate_by_mva(lower, upper - lower);
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dcache_mmu_disable();
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mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF);
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dcache_mmu_enable();
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lcdbase += 64*KiB;
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mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);
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printk(BIOS_DEBUG,
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"Initializing exynos VGA, base %p\n", (void *)lcdbase);
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memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
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ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase);
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}
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@ -33,6 +33,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select EXYNOS_DISPLAYPORT
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select CHROMEOS
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select DRIVER_TI_TPS65090
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_DO_NATIVE_VGA_INIT
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config MAINBOARD_DIR
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string
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@ -23,6 +23,7 @@
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#include <drivers/ti/tps65090/tps65090.h>
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#include <cbmem.h>
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#include <delay.h>
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#include <boot/coreboot_tables.h>
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <arch/gpio.h>
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@ -41,6 +42,41 @@
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#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
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#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
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int vbe_mode_info_valid(void);
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int vbe_mode_info_valid(void)
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{
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return 1;
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}
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void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
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void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
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{
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/*
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* The address returned points at the LCD colormap base. The
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* 64KiB offset points at the LCD base.
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*/
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framebuffer->physical_address =
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(u32)cbmem_find(CBMEM_ID_CONSOLE) + 64*KiB;
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printk(BIOS_SPEW, "%s: framebuffer->physical address is 0x%llx\n",
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__func__, framebuffer->physical_address);
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framebuffer->x_resolution = 1366;
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framebuffer->y_resolution = 768;
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framebuffer->bits_per_pixel = 16;
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framebuffer->bytes_per_line =
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(framebuffer->x_resolution * framebuffer->bits_per_pixel) / 8;
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framebuffer->red_mask_pos = 11;
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framebuffer->red_mask_size = 5;
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framebuffer->green_mask_pos = 6;
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framebuffer->green_mask_size = 5;
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framebuffer->blue_mask_pos = 0;
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framebuffer->blue_mask_size = 5;
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framebuffer->reserved_mask_pos = 0;
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framebuffer->reserved_mask_size = 0;
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}
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void hardwaremain(int boot_complete);
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void main(void)
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{
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