mediatek/mt8192: memlayout: Add DRAM DMA region

SPM DMA hardware requires a non-cacheable buffer to load SPM
firmware.

TEST=verified with SPM WIP patch.
     SPM PC stays at 0x3f4 after SPM firmware is loaded.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: If6e803da23126419a96ffc0337d35edd0e181871
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/mt8192/Makefile.inc

@@ -26,7 +26,7 @@ romstage-y += ../common/cbmem.c
 romstage-y += emi.c
 romstage-y += flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
-romstage-y += ../common/mmu_operations.c
+romstage-y += ../common/mmu_operations.c mmu_operations.c
 romstage-y += memory.c dramc_param.c ../common/memory_test.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 romstage-y += ../common/timer.c

src/soc/mediatek/mt8192/include/soc/memlayout.ld

@@ -14,6 +14,11 @@
 #define DRAM_INIT_CODE(addr, size) \
 	REGION(dram_init_code, addr, size, 4)
 
+#define DRAM_DMA(addr, size) \
+	REGION(dram_dma, addr, size, 4K) \
+	_ = ASSERT(size % 4K == 0, \
+		"DRAM DMA buffer should be multiple of smallest page size (4K)!");
+
 SECTIONS
 {
 	SRAM_START(0x00100000)
@@ -41,8 +46,9 @@ SECTIONS
 	SRAM_L2C_END(0x00280000)
 
 	DRAM_START(0x40000000)
-	POSTRAM_CBFS_CACHE(0x40000000, 2M)
-	RAMSTAGE(0x40200000, 256K)
+	DRAM_DMA(0x40000000, 1M)
+	POSTRAM_CBFS_CACHE(0x40100000, 2M)
+	RAMSTAGE(0x40300000, 256K)
 
 	BL31(0x54600000, 0x60000)
 }

src/soc/mediatek/mt8192/include/soc/symbols.h

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8192_SYMBOLS_H_
+#define _SOC_MEDIATEK_MT8192_SYMBOLS_H_
+#include <symbols.h>
+
+DECLARE_REGION(dram_dma)
+
+#endif /* _SOC_MEDIATEK_MT8192_SYMBOLS_H_ */

src/soc/mediatek/mt8192/mmu_operations.c

@@ -3,6 +3,7 @@
 #include <device/mmio.h>
 #include <soc/mcucfg.h>
 #include <soc/mmu_operations.h>
+#include <soc/symbols.h>
 
 DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
 DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
@@ -28,3 +29,10 @@ void mtk_soc_disable_l2c_sram(void)
 			MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
 	dsb();
 }
+
+/* mtk_soc_after_dram is called in romstage */
+void mtk_soc_after_dram(void)
+{
+	mmu_config_range(_dram_dma, REGION_SIZE(dram_dma),
+			 NONSECURE_UNCACHED_MEM);
+}