GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/alderlake/romstage: Skip GPIO configuration from FSP 

Set GpioOverride UPD to 1 to skip GPIO configuration in FSP phases

TEST=Able to build and boot ADLRVP to OS.

Change-Id: Ie965a85d9da9b6a23b385536313b852e66909cf4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2020-10-23 19:36:25 +05:30
parent a8ddc89d27
commit 28371e2826
1 changed files with 3 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/alderlake/romstage/fsp_params.c
View File

@ -157,6 +157,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev);
m_cfg->TmeEnable = CONFIG(INTEL_TME); m_cfg->TmeEnable = CONFIG(INTEL_TME);
/* Skip GPIO configuration from FSP */
m_cfg->GpioOverride = 0x1;
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)