src/soc/intel: Drop unneeded empty lines

Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/apollolake/cse.c

@@ -15,7 +15,6 @@
 #include <device/pci_ops.h>
 #include <stdint.h>
 
-
 #define MKHI_GROUP_ID_MCA			0x0a
 #define READ_FILE				0x02
 #define   READ_FILE_FLAG_DEFAULT		(1 << 0)

src/soc/intel/apollolake/gpio_glk.c

@@ -5,7 +5,6 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
-
 static const struct reset_mapping rst_map[] = {
 	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
 	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },

src/soc/intel/apollolake/include/soc/gpio_apl.h

@@ -27,7 +27,6 @@
 
 #define GPIO_MAX_NUM_PER_GROUP	32
 
-
 /* Host Software Pad Ownership Register.
  * The pins in the community are divided into 3 groups :
  * GPIO 0 ~ 31, GPIO 32 ~ 63, GPIO 64 ~ 95

src/soc/intel/apollolake/include/soc/gpio_glk.h

@@ -202,7 +202,6 @@
 #define GPIO_175			(AUDIO_OFFSET + 19)
 #define TOTAL_AUDIO_PADS		20
 
-
 /* SCC community pads */
 /* For SMBus, SD-Card, Clock, CNV/SDIO, eMMC */
 #define SCC_OFFSET			(AUDIO_OFFSET + 20)
@@ -297,11 +296,9 @@
 	(ALIGN_UP(NUM_SCC_PADS, GPIO_MAX_NUM_PER_GROUP) /	\
 		GPIO_MAX_NUM_PER_GROUP)
 
-
 #define NUM_GPI_STATUS_REGS		(NUM_N_GPI_REGS + NUM_NW_GPI_REGS \
 					+ NUM_AUDIO_GPI_REGS + NUM_SCC_GPI_REGS)
 
-
 /* Macros for translating a global pad offset to a local offset */
 #define PAD_NW(pad)			(pad - NW_OFFSET)
 #define PAD_N(pad)			(pad - N_OFFSET)

src/soc/intel/baytrail/chip.c

@@ -20,7 +20,6 @@ static struct device_operations cpu_bus_ops = {
 	.init             = baytrail_init_cpus,
 };
 
-
 static void enable_dev(struct device *dev)
 {
 	/* Set the operations if it is a special bus type */

src/soc/intel/baytrail/cpu.c

@@ -68,7 +68,6 @@ static const struct cpu_driver driver __cpu_driver = {
 	.id_table = cpu_table,
 };
 
-
 /*
  * MP and SMM loading initialization.
  */

src/soc/intel/baytrail/include/soc/lpc.h

@@ -16,7 +16,6 @@
 #define UART_CONT	0x80
 #define RCBA		0xf0
 
-
 #define RID_A_STEPPING_START 1
 #define RID_B_STEPPING_START 5
 #define RID_C_STEPPING_START 0xe

src/soc/intel/baytrail/perf_power.c

@@ -262,7 +262,6 @@ E(SEC,  0x88,     MASK_VAL(0,    0,    0x0)),    //vlv.sec.clk_gate_dis.sb_cg_di
 REG_SCRIPT_END,
 };
 
-
 static void perf_power(void *unused)
 {
 	printk(BIOS_DEBUG, "Applying perf/power settings.\n");

src/soc/intel/baytrail/pmutil.c

@@ -230,7 +230,6 @@ void disable_all_gpe(void)
 	disable_gpe(~0);
 }
 
-
 static uint32_t reset_gpe_status(void)
 {
 	uint16_t pmbase = get_pmbase();

src/soc/intel/baytrail/scc.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #include <acpi/acpi_gnvs.h>
 #include <console/console.h>
 #include <device/device.h>

src/soc/intel/baytrail/southcluster.c

@@ -507,7 +507,6 @@ static void southcluster_inject_dsdt(const struct device *device)
 	}
 }
 
-
 static struct device_operations device_ops = {
 	.read_resources		= sc_read_resources,
 	.set_resources		= pci_dev_set_resources,

src/soc/intel/braswell/bootblock/bootblock.c

@@ -105,7 +105,6 @@ static void setup_mmconfig(void)
 	pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
 }
 
-
 void bootblock_soc_early_init(void)
 {
 	/* Allow memory-mapped PCI config access */

src/soc/intel/braswell/chip.c

@@ -22,7 +22,6 @@ static struct device_operations cpu_bus_ops = {
 	.init             = soc_init_cpus
 };
 
-
 static void enable_dev(struct device *dev)
 {
 	/* Set the operations if it is a special bus type */

src/soc/intel/braswell/chip.h

@@ -39,7 +39,6 @@ enum usb_comp_bg_value {
 	USB_COMP_BG_675_MV = 0,
 };
 
-
 struct soc_intel_braswell_config {
 	uint8_t enable_xdp_tap;
 	uint8_t clkreq_enable;

src/soc/intel/braswell/cpu.c

@@ -71,7 +71,6 @@ static const struct cpu_driver driver __cpu_driver = {
 	.id_table = cpu_table,
 };
 
-
 /*
  * MP and SMM loading initialization.
  */

src/soc/intel/braswell/gpio.c

@@ -8,7 +8,6 @@
 #include <soc/pm.h>
 #include <soc/smm.h>
 
-
 #define GPIO_DEBUG
 
 /* gpio map to pad number LUTs */
@@ -29,7 +28,6 @@ static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = {
 	66, 67, 68, 69, 75, 76, 77, 78, 79, 80,
 	81, 82, 83, 84, 85 };
 
-
 static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = {
 	 0,  1,  2,  3,  4,  5,  6,  7, 15, 16,
 	17, 18, 19, 20, 21, 22, 30, 31, 32, 33,
@@ -156,7 +154,6 @@ static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
 	smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
 }
 
-
 static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank *community)
 {
 	const struct soc_gpio_map *config;
@@ -228,7 +225,6 @@ static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank
 	write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask);
 }
 
-
 void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
 {
 	if (config) {

src/soc/intel/braswell/include/soc/gpio.h

@@ -69,7 +69,6 @@
 #define GP_FAMILY_CONF_REG(community, family)		\
 (COMMUNITY_BASE(community) + 0x1094 + 0x80 * family)
 
-
 /* Value written into pad control reg 0 */
 #define PAD_CONTROL_REG0_TRISTATE      (PAD_CONFIG0_DEFAULT|PAD_GPIOFG_HI_Z)
 

src/soc/intel/braswell/include/soc/irq.h

@@ -126,7 +126,6 @@
 #define GPIO_S0_DED_IRQ(slot)		_GPIO_N_DED_IRQ(slot)
 #define GPIO_S5_DED_IRQ(slot)		_GPIO_E_DED_IRQ(slot)
 
-
 /* PIC IRQ settings. */
 #define PIRQ_PIC_IRQDISABLE		0x80
 #define PIRQ_PIC_IRQ3			0x3

src/soc/intel/braswell/lpc_init.c

@@ -21,7 +21,6 @@
 #define LPC_AD3_MMIO_OFFSET	LPC_GPIO_OFFSET(50)
 #define LPC_AD1_MMIO_OFFSET	LPC_GPIO_OFFSET(52)
 
-
 /* Value written into pad control reg 0 in early init */
 #define PAD_CFG0_NATIVE(mode, term, inv_rx_tx) (PAD_GPIO_DISABLE \
 				| PAD_GPIOFG_HI_Z \

src/soc/intel/braswell/lpe.c

@@ -102,7 +102,6 @@ static void setup_codec_clock(struct device *dev)
 	/* Default to always running. */
 	reg |= CLK_CTL_ON;
 
-
 	printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
 
 	clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);

src/soc/intel/braswell/pmutil.c

@@ -229,7 +229,6 @@ void disable_all_gpe(void)
 	disable_gpe(~0);
 }
 
-
 static uint32_t reset_gpe_status(void)
 {
 	uint16_t pmbase = get_pmbase();

src/soc/intel/braswell/romstage/romstage.c

@@ -11,7 +11,6 @@
 
 #include "../chip.h"
 
-
 static struct chipset_power_state power_state;
 
 static void migrate_power_state(int is_recovery)
@@ -83,7 +82,6 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	return prev_sleep_state;
 }
 
-
 /* SOC initialization after RAM is enabled */
 void soc_after_ram_init(struct romstage_params *params)
 {

src/soc/intel/braswell/scc.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #include <acpi/acpi_gnvs.h>
 #include <console/console.h>
 #include <device/device.h>

src/soc/intel/braswell/smihandler.c

@@ -100,7 +100,6 @@ static void tristate_gpios(uint32_t val)
 	write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val);
 }
 
-
 static void southbridge_smi_sleep(void)
 {
 	uint32_t reg32;

src/soc/intel/broadwell/finalize.c

@@ -65,7 +65,6 @@ const struct reg_script pch_finalize_script[] = {
 	/* PMSYNC */
 	REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
 
-
 	REG_SCRIPT_END
 };
 

src/soc/intel/broadwell/include/soc/pei_data.h

@@ -63,7 +63,6 @@ struct usb3_port_setting {
 #define PEI_DIMM_INFO_PART_NUMBER_SIZE	19
 #define PEI_DIMM_INFO_TOTAL		8	/* Maximum num of dimm is 8 */
 
-
 /**
  * This table is filled by the MRC blob and used to populate the mem_info
  * struct, which is placed in CBMEM and then used to generate SMBIOS type

src/soc/intel/broadwell/me_status.c

@@ -13,7 +13,6 @@
 		(__array__)[(__index__)] : \
 		(__default__))
 
-
 static inline void me_read_dword_ptr(void *ptr, int offset)
 {
 	u32 dword = pci_read_config32(PCH_DEV_ME, offset);

src/soc/intel/broadwell/pmutil.c

@@ -52,7 +52,6 @@ static void print_gpio_status(u32 status, int start)
 	}
 }
 
-
 /*
  * PM1_CNT
  */
@@ -73,7 +72,6 @@ void disable_pm1_control(u32 mask)
 	outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
 }
 
-
 /*
  * PM1
  */
@@ -122,7 +120,6 @@ void enable_pm1(u16 events)
 	outw(events, ACPI_BASE_ADDRESS + PM1_EN);
 }
 
-
 /*
  * SMI
  */
@@ -193,7 +190,6 @@ void disable_smi(u32 mask)
 	outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
 }
 
-
 /*
  * ALT_GP_SMI
  */
@@ -244,7 +240,6 @@ void enable_alt_smi(u32 mask)
 	outl(alt_en, GPIO_BASE_ADDRESS + GPIO_ALT_GPI_SMI_EN);
 }
 
-
 /*
  * TCO
  */
@@ -312,7 +307,6 @@ void enable_tco_sci(void)
 	enable_gpe(TCOSCI_EN);
 }
 
-
 /*
  * GPE0
  */

src/soc/intel/broadwell/sata.c

@@ -200,7 +200,6 @@ static void sata_init(struct device *dev)
 				<< SATA_DTLE_EDGE_SHIFT);
 	}
 
-
 	/*
 	 * Additional Programming Requirements for Power Optimizer
 	 */

src/soc/intel/broadwell/smihandler.c

@@ -465,7 +465,6 @@ static void southbridge_smi_monitor(void)
 			mask |= (0xff << ((i - 16) << 2));
 	}
 
-
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
 		if (gnvs && gnvs->smif)

src/soc/intel/broadwell/smmrelocate.c

@@ -18,7 +18,6 @@
 #include <soc/pci_devs.h>
 #include <soc/systemagent.h>
 
-
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,
 				struct smm_relocation_params *relo_params)

src/soc/intel/cannonlake/bootblock/pch.c

@@ -89,7 +89,6 @@ void bootblock_pch_early_init(void)
 	soc_config_pwrmbase();
 }
 
-
 static void soc_config_acpibase(void)
 {
 	uint32_t pmc_reg_value;

src/soc/intel/cannonlake/chip.h

@@ -113,7 +113,6 @@ struct soc_intel_cannonlake_config {
 		SaGv_Enabled,
 	} SaGv;
 
-
 	/* Rank Margin Tool. 1:Enable, 0:Disable */
 	uint8_t RMT;
 

src/soc/intel/cannonlake/fsp_params.c

@@ -370,7 +370,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 			params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
 	};
 
-
 	/* eMMC and SD */
 	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
 	if (!dev)

src/soc/intel/cannonlake/include/soc/pch.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_CANNONLAKE_PCH_H_
 #define _SOC_CANNONLAKE_PCH_H_
 
-
 #define PCH_H				1
 #define PCH_LP				2
 #define PCH_UNKNOWN_SERIES		0xFF

src/soc/intel/cannonlake/include/soc/sata.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _SOC_SATA_H_
 #define _SOC_SATA_H_
 

src/soc/intel/cannonlake/include/soc/usb.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _SOC_USB_H_
 #define _SOC_USB_H_
 

src/soc/intel/cannonlake/smmrelocate.c

@@ -19,7 +19,6 @@
 #include <soc/systemagent.h>
 #include "chip.h"
 
-
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,
 				struct smm_relocation_params *relo_params)

src/soc/intel/cannonlake/vr_config.c

@@ -322,7 +322,6 @@ static const struct vr_lookup vr_config_icc[] = {
 	VR_REFITEM_ICC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
 };
 
-
 VR_CONFIG_LL(PCI_DEVICE_ID_INTEL_CNL_ID_U) {
 	{  0, value_not_set, VR_CFG_ALL_DOMAINS_LOADLINE(10.3, 2.4, 2.0, 2.0) },
 };
@@ -442,8 +441,6 @@ static const struct vr_lookup vr_config_ll[] = {
 	VR_REFITEM_LL(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
 };
 
-
-
 VR_CONFIG_TDC(PCI_DEVICE_ID_INTEL_CFL_ID_S) {
 	{ 58, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 33, 30, 30) },
 	{ 54, value_not_set, VR_CFG_ALL_DOMAINS_TDC(10, 31, 30, 30) },
@@ -557,7 +554,6 @@ static const struct vr_lookup vr_config_tdc[] = {
 	VR_REFITEM_TDC(PCI_DEVICE_ID_INTEL_CML_S_G0G1_P0P1_6_2),
 };
 
-
 static uint16_t get_sku_voltagelimit(int domain)
 {
 	return 1520;

src/soc/intel/common/block/fast_spi/fast_spi.c

@@ -101,7 +101,6 @@ void fast_spi_set_lock_enable(void)
 {
 	fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_LOCK_ENABLE);
 
-
 	fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
 }
 

src/soc/intel/common/block/fast_spi/fast_spi_flash.c

@@ -154,7 +154,6 @@ static size_t get_xfer_len(const struct spi_flash *flash, uint32_t addr,
 	return xfer_len;
 }
 
-
 static int fast_spi_flash_erase(const struct spi_flash *flash,
 				uint32_t offset, size_t len)
 {

src/soc/intel/common/block/include/intelblocks/gpio.h

@@ -81,7 +81,6 @@ struct reset_mapping {
 	uint32_t chipset;
 };
 
-
 /* Structure describes the groups within each community */
 struct pad_group {
 	int		first_pad; /* offset of first pad of the group relative

src/soc/intel/common/block/include/intelblocks/pcie_rp.h

@@ -3,7 +3,6 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 #define SOC_INTEL_COMMON_BLOCK_PCIE_RP_H
 
-
 /*
  * The PCIe Root Ports usually come in groups of up to 8 PCI-device
  * functions.

src/soc/intel/common/block/include/intelblocks/pcr.h

@@ -46,7 +46,6 @@ struct pcr_sbi_msg {
 	uint16_t fid; /* 0x0B - Function ID */
 };
 
-
 /*
  * API to perform sideband communication
  *

src/soc/intel/common/block/lpc/lpc_lib.c

@@ -236,7 +236,6 @@ void lpc_set_serirq_mode(enum serirq_mode mode)
 	pci_write_config8(dev, LPC_SERIRQ_CTL, scnt);
 }
 
-
 void lpc_io_setup_comm_a_b(void)
 {
 	/* ComA Range 3F8h-3FFh [2:0] */

src/soc/intel/common/block/smbus/smbuslib.h

@@ -3,7 +3,6 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H
 #define SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H
 
-
 /* SMBus IO Base Address */
 #define SMBUS_IO_BASE	0xefa0
 

src/soc/intel/common/block/smm/smihandler.c

@@ -169,7 +169,6 @@ static void busmaster_disable_on_bus(int bus)
 	}
 }
 
-
 void smihandler_southbridge_sleep(
 	const struct smm_save_state_ops *save_state_ops)
 {

src/soc/intel/common/block/systemagent/systemagent.c

@@ -146,7 +146,6 @@ void sa_fill_gnvs(struct global_nvs *gnvs)
 	       gnvs->a4gb, gnvs->a4gs);
 }
 
-
 static void sa_get_mem_map(struct device *dev, uint64_t *values)
 {
 	int i;

src/soc/intel/common/block/systemagent/systemagent_def.h

@@ -3,7 +3,6 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H
 #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H
 
-
 /* Device 0:0.0 PCI configuration space */
 
 /* GMCH Graphics Control Register */

src/soc/intel/common/pch/include/intelpch/lockdown.h

@@ -3,7 +3,6 @@
 #ifndef SOC_INTEL_COMMON_PCH_LOCKDOWN_H
 #define SOC_INTEL_COMMON_PCH_LOCKDOWN_H
 
-
 /*
  * This function will get lockdown config specific to soc.
  *

src/soc/intel/denverton_ns/include/soc/gpio.h

@@ -9,7 +9,6 @@
 
 #define GPIO_MAX_NUM_PER_GROUP	32
 
-
 #define NUM_NC_GPI_REGS	\
 	(ALIGN_UP(V_PCH_GPIO_NC_PAD_MAX, GPIO_MAX_NUM_PER_GROUP) \
 	/ GPIO_MAX_NUM_PER_GROUP)
@@ -29,7 +28,6 @@
 #define NUM_GPI_STATUS_REGS (NUM_NC_GPI_REGS + NUM_SC_DFX_GPI_REGS +\
 			     NUM_SC0_GPI_REGS + NUM_SC1_GPI_REGS)
 
-
 #define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
 
 #include <intelblocks/gpio.h>/* intelblocks/gpio.h depends on definitions in

src/soc/intel/denverton_ns/include/soc/hob_mem.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _DENVERTON_NS_HOB_MEM_H
 #define _DENVERTON_NS_HOB_MEM_H
 

src/soc/intel/denverton_ns/include/soc/pci_devs.h

@@ -5,7 +5,6 @@
 
 /* All these devices live on bus 0 with the associated device and function */
 
-
 #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func)
 
 #if !defined(__SIMPLE_DEVICE__)

src/soc/intel/icelake/chip.h

@@ -82,7 +82,6 @@ struct soc_intel_icelake_config {
 		SaGv_Enabled,
 	} SaGv;
 
-
 	/* Rank Margin Tool. 1:Enable, 0:Disable */
 	uint8_t RMT;
 

src/soc/intel/icelake/gpio.c

@@ -49,14 +49,12 @@ static const struct pad_group icl_community2_groups[] = {
 	INTEL_GPP(GPD0, GPD0, GPD11),				/* GPD */
 };
 
-
 static const struct pad_group icl_community4_groups[] = {
 	INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 224),		/* GPP_C */
 	INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 256),		/* GPP_E */
 	INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8),
 };
 
-
 static const struct pad_group icl_community5_groups[] = {
 	INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 288),		/* GPP_R */
 	INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320),		/* GPP_S */

src/soc/intel/icelake/include/soc/gpio_defs.h

@@ -8,7 +8,6 @@
 #endif
 #include <soc/gpio_soc_defs.h>
 
-
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
 
 #define NUM_GPIO_COMx_GPI_REGS(n)	\

src/soc/intel/icelake/include/soc/gpio_soc_defs.h

@@ -167,7 +167,6 @@
 
 #define NUM_GPIO_COM1_PADS	(GPP_F19 - GPP_H0 + 1)
 
-
 /* Group GPD  */
 #define GPD0		123
 #define GPD1		124
@@ -184,7 +183,6 @@
 
 #define NUM_GPIO_COM2_PADS	(GPD11 - GPD0 + 1)
 
-
 /* Group C */
 #define GPP_C0		135
 #define GPP_C1		136

src/soc/intel/icelake/include/soc/pch.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_ICELAKE_PCH_H_
 #define _SOC_ICELAKE_PCH_H_
 
-
 #define PCH_H				1
 #define PCH_LP				2
 #define PCH_UNKNOWN_SERIES		0xFF

src/soc/intel/icelake/include/soc/usb.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _SOC_USB_H_
 #define _SOC_USB_H_
 

src/soc/intel/icelake/smmrelocate.c

@@ -18,7 +18,6 @@
 #include <soc/pci_devs.h>
 #include <soc/soc_chip.h>
 
-
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,
 				struct smm_relocation_params *relo_params)

src/soc/intel/jasperlake/gpio.c

@@ -56,14 +56,12 @@ static const struct pad_group jsl_community2_groups[] = {
 	INTEL_GPP(GPD0, GPIO_RSVD_14, GPIO_RSVD_17),
 };
 
-
 static const struct pad_group jsl_community4_groups[] = {
 	INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_18, GPIO_RSVD_23),
 	INTEL_GPP_BASE(GPIO_RSVD_18, GPP_E0, GPP_E23, 288),		/* GPP_E */
 	INTEL_GPP(GPIO_RSVD_18, GPIO_RSVD_24, GPIO_RSVD_36),
 };
 
-
 static const struct pad_group jsl_community5_groups[] = {
 	INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 320),		/* GPP_G */
 };

src/soc/intel/jasperlake/include/soc/espi.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_JASPERLAKE_ESPI_H_
 #define _SOC_JASPERLAKE_ESPI_H_
 
-
 /* PCI Configuration Space (D31:F0): ESPI */
 #define SCI_IRQ_SEL		(7 << 0)
 #define SCIS_IRQ9		0

src/soc/intel/jasperlake/include/soc/gpio.h

@@ -6,7 +6,6 @@
 #include <soc/gpio_defs.h>
 #include <intelblocks/gpio.h>
 
-
 #define CROS_GPIO_NAME		"INT34C8"
 #define CROS_GPIO_COMM0_NAME    "INT34C8:00"
 #define CROS_GPIO_COMM1_NAME    "INT34C8:01"

src/soc/intel/jasperlake/include/soc/gpio_defs.h

@@ -8,7 +8,6 @@
 #endif
 #include <soc/gpio_soc_defs.h>
 
-
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
 
 #define NUM_GPIO_COMx_GPI_REGS(n)	\

src/soc/intel/jasperlake/include/soc/pch.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_JASPERLAKE_PCH_H_
 #define _SOC_JASPERLAKE_PCH_H_
 
-
 #define PCIE_CLK_NOTUSED		0xFF
 #define PCIE_CLK_LAN			0x70
 #define PCIE_CLK_FREE			0x80

src/soc/intel/jasperlake/include/soc/usb.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _SOC_USB_H_
 #define _SOC_USB_H_
 

src/soc/intel/jasperlake/pmutil.c

@@ -156,7 +156,6 @@ uintptr_t soc_read_pmc_base(void)
 	return (uintptr_t)pmc_mmio_regs();
 }
 
-
 uint32_t *soc_pmc_etr_addr(void)
 {
 	return (uint32_t *)(soc_read_pmc_base() + ETR);

src/soc/intel/quark/acpi.c

@@ -10,7 +10,6 @@ unsigned long acpi_fill_madt(unsigned long current)
 	return current;
 }
 
-
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	return current;

src/soc/intel/quark/include/soc/QuarkNcSocId.h

@@ -66,7 +66,6 @@
 #define   QUARK2_MC_DEVICE_ID     0x12C0
 #define   QNC_MC_REV_ID_A0      0x00
 
-
 //
 // MCR - B0:D0:F0:RD0h (WO)- Message control register (Datasheet 12.5)
 // [31:24] Message opcode - D0 read; E0 write;
@@ -119,7 +118,6 @@
 #define QUARK_OPCODE_IO_READ           0x02 // Message bus "IO read" opcode
 #define QUARK_OPCODE_IO_WRITE          0x03 // Message bus "IO write" opcode
 
-
 #define QUARK_DRAM_BASE_ADDR_READY     0x78 // Message bus "RMU Main binary
 					    // shadow" opcode
 
@@ -501,7 +499,6 @@
 #define   B_QNC_PM1BLK_PM1S_TO            (BIT0)
 #define    N_QNC_PM1BLK_PM1S_RTC           10
 
-
 #define R_QNC_PM1BLK_PM1E               0x02
 #define  S_QNC_PM1BLK_PM1E               2
 #define   B_QNC_PM1BLK_PM1E_PWAKED        (BIT14)

src/soc/intel/quark/include/soc/acpi.h

@@ -6,5 +6,4 @@
 #include <acpi/acpi.h>
 #include <acpi/acpigen.h>
 
-
 #endif /* _SOC_ACPI_H_ */

src/soc/intel/quark/include/soc/storage_test.h

@@ -22,7 +22,6 @@ void storage_test_complete(struct device *dev, uint32_t previous_bar,
 	uint16_t previous_command);
 #endif
 
-
 /* Logging support */
 struct log_entry {
 	struct mono_time time;

src/soc/intel/skylake/chip.c

@@ -295,7 +295,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->Device4Enable = dev && dev->enabled;
 	params->EnableTcoTimer = !config->PmTimerDisabled;
 
-
 	tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
 	tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
 	tconfig->PowerLimit4 = config->PowerLimit4;

src/soc/intel/skylake/chip.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _SOC_CHIP_H_
 #define _SOC_CHIP_H_
 

src/soc/intel/skylake/cpu.c

@@ -32,7 +32,6 @@ static void configure_isst(void)
 	config_t *conf = config_of_soc();
 	msr_t msr;
 
-
 	if (conf->speed_shift_enable) {
 		/*
 		* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
@@ -58,7 +57,6 @@ static void configure_misc(void)
 	config_t *conf = config_of_soc();
 	msr_t msr;
 
-
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */

src/soc/intel/skylake/gpio.c

@@ -5,7 +5,6 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
-
 static const struct reset_mapping rst_map[] = {
 	{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30},
 	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},

src/soc/intel/skylake/include/soc/gpio_soc_defs.h

@@ -209,5 +209,4 @@
 
 #define NUM_GPIO_COM2_PADS	(GPD11 - GPD0 + 1)
 
-
 #endif /* _SOC_GPIO_SOC_DEFS_H_ */

src/soc/intel/skylake/include/soc/usb.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _SOC_USB_H_
 #define _SOC_USB_H_
 

src/soc/intel/skylake/include/soc/vr_config.h

@@ -80,7 +80,6 @@ enum vr_domain {
 		[VR_GT_SLICED]    = VR_CFG_MOHMS(gt_sl),	\
 	}
 
-
 void fill_vr_domain_config(void *params,
 			int domain, const struct vr_config *cfg);
 #endif

src/soc/intel/skylake/me.c

@@ -10,7 +10,6 @@
 #include <soc/me.h>
 #include <soc/pci_devs.h>
 
-
 /* HFSTS1[3:0] Current Working State Values */
 static const char *const me_cws_values[] = {
 	[ME_HFS_CWS_RESET]	= "Reset",

src/soc/intel/skylake/smmrelocate.c

@@ -19,7 +19,6 @@
 #include <soc/systemagent.h>
 #include "chip.h"
 
-
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,
 				struct smm_relocation_params *relo_params)

src/soc/intel/tigerlake/include/soc/espi.h

@@ -9,7 +9,6 @@
 #ifndef _SOC_TIGERLAKE_ESPI_H_
 #define _SOC_TIGERLAKE_ESPI_H_
 
-
 /* PCI Configuration Space (D31:F0): ESPI */
 #define SCI_IRQ_SEL		(7 << 0)
 #define SCIS_IRQ9		0

src/soc/intel/tigerlake/include/soc/gpio.h

@@ -6,7 +6,6 @@
 #include <soc/gpio_defs.h>
 #include <intelblocks/gpio.h>
 
-
 #define CROS_GPIO_DEVICE_NAME	"INT34C5:00"
 
 #endif

src/soc/intel/tigerlake/include/soc/gpio_defs.h

@@ -109,7 +109,6 @@
 #define GPP_R6_IRQ				0x5E
 #define GPP_R7_IRQ				0x5F
 
-
 /* Group D */
 #define GPD0_IRQ				0x60
 #define GPD1_IRQ				0x61
@@ -182,7 +181,6 @@
 #define GPP_D18_IRQ				0x3E
 #define GPP_D19_IRQ				0x3F
 
-
 /* Group U */
 #define GPP_U0_IRQ				0x40
 #define GPP_U1IRQ				0x41
@@ -205,7 +203,6 @@
 #define GPP_U18_IRQ				0x52
 #define GPP_U19_IRQ				0x53
 
-
 #define GPP_VGPIO4_IRQ				0x54
 
 /* Group F */
@@ -260,8 +257,6 @@
 #define GPP_C22_IRQ				0x24
 #define GPP_C23_IRQ				0x25
 
-
-
 /* Group E */
 #define GPP_E0_IRQ				0x26
 #define GPP_E1_IRQ				0x27

src/soc/intel/tigerlake/include/soc/pch.h

@@ -3,7 +3,6 @@
 #ifndef _SOC_TIGERLAKE_PCH_H_
 #define _SOC_TIGERLAKE_PCH_H_
 
-
 #define PCIE_CLK_NOTUSED		0xFF
 #define PCIE_CLK_LAN			0x70
 #define PCIE_CLK_FREE			0x80

src/soc/intel/tigerlake/include/soc/usb.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-
 #ifndef _SOC_USB_H_
 #define _SOC_USB_H_
 

src/soc/intel/tigerlake/pmutil.c

@@ -11,7 +11,6 @@
  * Chapter number: 4
  */
 
-
 #define __SIMPLE_DEVICE__
 
 #include <device/mmio.h>
@@ -163,7 +162,6 @@ uintptr_t soc_read_pmc_base(void)
 	return (uintptr_t)pmc_mmio_regs();
 }
 
-
 uint32_t *soc_pmc_etr_addr(void)
 {
 	return (uint32_t *)(soc_read_pmc_base() + ETR);

src/soc/intel/xeon_sp/cpx/chip.c

@@ -450,7 +450,6 @@ static void xeonsp_pci_domain_read_resources(struct device *dev)
 		}
 	}
 
-
 	/* assign resources */
 	assign_stack_resources(&stack_info, dev, NULL);
 

src/soc/intel/xeon_sp/cpx/cpu.c

@@ -44,7 +44,6 @@ static void xeon_configure_mca(void)
 	mca_configure();
 }
 
-
 void get_microcode_info(const void **microcode, int *parallel)
 {
 	*microcode = intel_mp_current_microcode();

src/soc/intel/xeon_sp/cpx/soc_util.c

@@ -41,7 +41,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void)
 	return *memmap_addr;
 }
 
-
 void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits,
 	uint8_t *package, uint8_t *core, uint8_t *thread)
 {
@@ -135,7 +134,6 @@ void xeonsp_init_cpu_config(void)
 		}
 	}
 
-
 	/* update apic_id, node_id in sorted order */
 	num_apics = 0;
 	get_core_thread_bits(&core_bits, &thread_bits);

src/soc/intel/xeon_sp/include/soc/iomap.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-
 #ifndef _SOC_IOMAP_H_
 #define _SOC_IOMAP_H_
 

src/soc/intel/xeon_sp/include/soc/romstage.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-
 #ifndef _SOC_ROMSTAGE_H_
 #define _SOC_ROMSTAGE_H_
 

src/soc/intel/xeon_sp/skx/chip.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-
 #ifndef _SOC_CHIP_H_
 #define _SOC_CHIP_H_
 

src/soc/intel/xeon_sp/skx/cpu.c

@@ -221,7 +221,6 @@ static const struct mp_ops mp_ops = {
 	.post_mp_init = post_mp_init,
 };
 
-
 void xeon_sp_init_cpus(struct device *dev)
 {
 	FUNC_ENTER();

src/soc/intel/xeon_sp/skx/include/soc/acpi.h

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-
 #ifndef _SOC_ACPI_H_
 #define _SOC_ACPI_H_
 

src/soc/intel/xeon_sp/skx/soc_util.c

@@ -415,7 +415,6 @@ void xeonsp_init_cpu_config(void)
 		}
 	}
 
-
 	/* update apic_id, node_id in sorted order */
 	num_apics = 0;
 	get_core_thread_bits(&core_bits, &thread_bits);

src/soc/intel/xeon_sp/skx/upd_display.c

@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-
 #include <console/console.h>
 #include <fsp/util.h>
 #include <lib.h>