From 285cbb38f789a8502376d18be1001e7d01824491 Mon Sep 17 00:00:00 2001
From: Frank Wu <frank_wu@compal.corp-partner.google.com>
Date: Tue, 25 Aug 2020 12:43:07 +0800
Subject: [PATCH] mb/google/volteer/var/halvor: Update TBT2 setting for Halvor

Enable TBT2 setting in overridetree.cb based on schematic.

BUG=b:165175296, b:166060548
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I23ecf76a3c2f631211b0ae2898707c68862b374b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
---
 src/mainboard/google/volteer/variants/halvor/overridetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
index 2db3b96213..2ef2e42634 100644
--- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb
@@ -19,6 +19,7 @@ chip soc/intel/tigerlake
 
 	device domain 0 on
 		device pci 07.2 on end # TBT_PCIe2
+		device pci 0d.3 on end # TBT DMA1			0x9A1D
 		device pci 15.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""