soc/amd/common/amdblocks/psp: move MSR_PSP_ADDR to include/cpu/amd/msr.h

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/include/cpu/amd/msr.h

@@ -78,6 +78,7 @@
 #define LS_CFG2_MSR			0xC001102D
 #define IBS_OP_DATA3_MSR		0xC0011037
 #define S3_RESUME_EIP_MSR		0xC00110E0
+#define MSR_PSP_ADDR			0xc00110a2
 
 #define MSR_PATCH_LEVEL			0x0000008B
 #define CORE_PERF_BOOST_CTRL		0x15c

src/soc/amd/common/block/include/amdblocks/psp.h

@@ -3,8 +3,6 @@
 #ifndef AMD_BLOCK_PSP_H
 #define AMD_BLOCK_PSP_H
 
-#define MSR_PSP_ADDR		0xc00110a2
-
 /* Get the mailbox base address - specific to family of device. */
 void *soc_get_mbox_address(void);
 

src/soc/amd/common/block/psp/psp_gen2.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <console/console.h>
+#include <cpu/amd/msr.h>
 #include <cpu/x86/msr.h>
 #include <device/mmio.h>
 #include <timer.h>

src/soc/amd/stoneyridge/cpu.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/smm.h>
+#include <cpu/amd/msr.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/mtrr.h>
@@ -15,7 +16,6 @@
 #include <soc/smi.h>
 #include <soc/iomap.h>
 #include <console/console.h>
-#include <amdblocks/psp.h>
 
 /*
  * MP and SMM loading initialization.

src/soc/amd/stoneyridge/psp.c

@@ -3,6 +3,7 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
+#include <cpu/amd/msr.h>
 #include <cpu/x86/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/northbridge.h>