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mainboard/amd/bilby: Add Bilby CRB board

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Bilby is the reference board for AMD Raven, Raven2 and Picasso APUs.
Bilby mainboard code is taken from mandolin variant Cereme.
These new files are a renamed copy and subsequent patches will be
applied to create a working bilby implementation.

Change-Id: I426966d782e259a971ec36bac2498bc62b4ce7e2
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Ritul Guru 2021-02-05 23:53:28 +05:30 committed by Felix Held
parent 65819cd364
commit 286c2f6d4a
16 changed files with 828 additions and 0 deletions
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136
src/mainboard/amd/bilby/Kconfig Normal file
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# SPDX-License-Identifier: GPL-2.0-only
if BOARD_AMD_BILBY
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_AMD_COMMON_BLOCK_USE_ESPI
select SOC_AMD_PICASSO
select BOARD_ROMSIZE_KB_16384
select AZALIA_PLUGIN_SUPPORT
select HAVE_ACPI_RESUME
select DRIVERS_UART_ACPI
select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD
config FMDFILE
string
default "src/mainboard/amd/bilby/board.fmd"
config AMD_LPC_DEBUG_CARD
bool "Enable LPC-Serial debug card on the debug header"
default n
select BILBY_LPC
select SUPERIO_SMSC_SIO1036
help
AMD's debug card contains an SMSC SIO1036 device which provides an
I/O-mapped UART in the system. This is mutually exclusive with
AMD_SOC_CONSOLE_UART which selects the SoC's integrated memory-mapped
UART for coreboot console output.
choice
prompt "SMSC/Microchip 1036 SuperIO config address"
depends on SUPERIO_SMSC_SIO1036
default BILBY_SMSC_SIO1036_BASE_164E
config BILBY_SMSC_SIO1036_BASE_4E
bool "0x4e/0x4d base address"
config BILBY_SMSC_SIO1036_BASE_164E
bool "0x164e/0x164d base address"
endchoice
config SUPERIO_ADDR_BASE
hex
default 0x4e if BILBY_SMSC_SIO1036_BASE_4E
default 0x164e if BILBY_SMSC_SIO1036_BASE_164E
config CBFS_SIZE
hex
default 0xfcf000 # Maximum size for the Bilby FMAP
config MAINBOARD_DIR
string
default "amd/bilby"
config MAINBOARD_PART_NUMBER
string
default "BILBY"
config DEVICETREE
string
default "devicetree.cb"
config ONBOARD_VGA_IS_PRIMARY
bool
default y
config AMD_FWM_POSITION_INDEX
int
default 4
help
TODO: might need to be adapted for better placement of files in cbfs
config MANDOLIN_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
default n
config MANDOLIN_MCHP_FW_FILE
string
depends on MANDOLIN_HAVE_MCHP_FW
default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN
default "3rdparty/blobs/mainboard/amd/mandolin/EC_cereme.bin" if BOARD_AMD_BILBY
help
The EC firmware blob is usually the first 128kByte of the stock
firmware image.
if !AMD_LPC_DEBUG_CARD
choice
prompt "State of IOMux for LPC/eMMC signals"
default BILBY_IOMUX_USE_EMMC
help
Bilby is designed to use either LPC or eMMC signals. Use this
selection to determine which are configured for this image.
config BILBY_IOMUX_USE_LPC
bool "LPC signals"
config BILBY_IOMUX_USE_EMMC
bool "eMMC signals"
endchoice
endif # !AMD_LPC_DEBUG_CARD
config BILBY_LPC
bool
default y if BILBY_IOMUX_USE_LPC
help
Picasso's LPC bus signals are MUXed with some of the EMMC signals.
Select this option if LPC signals are required.
#TODO: remove this hack to not break graphics in combination with SeaBIOS
config VGA_BIOS_DGPU_ID
string
default "1002,15d8"
help
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
config VGA_BIOS_DGPU_FILE
string
default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin"
config EFS_SPI_READ_MODE
int
default 0 if EM100
default 3
config EFS_SPI_SPEED
int
default 3 if EM100
default 0
config EFS_SPI_MICRON_FLAG
int
default 0
endif # BOARD_AMD_BILBY

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src/mainboard/amd/bilby/Kconfig.name Normal file
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config BOARD_AMD_BILBY
bool "Bilby"

33
src/mainboard/amd/bilby/Makefile.inc Normal file
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# SPDX-License-Identifier: GPL-2.0-only
bootblock-y += bootblock.c
bootblock-y += early_gpio.c
ramstage-y += gpio.c
ramstage-y += port_descriptors.c
ifneq ($(CONFIG_BILBY_LPC),y)
ramstage-y += emmc_gpio.c
endif
ifeq ($(CONFIG_BOARD_AMD_BILBY),y)
APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_bilby.bin
endif
ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y)
$(call add_intermediate, add_mchp_fw)
$(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MANDOLIN_MCHP_FW_FILE) --fill-upward
else
files_added:: warn_no_mchp
endif # CONFIG_MANDOLIN_HAVE_MCHP_FW
PHONY+=warn_no_mchp
warn_no_mchp:
printf "\n\t** WARNING **\n"
printf "coreboot has been built without an the Microchip EC.\n"
printf "Do not flash this image. Your Mandolin's power button\n"
printf "will not respond when you press it.\n\n"
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/acpi

8
src/mainboard/amd/bilby/board.fmd Normal file
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FLASH@0xFF000000 16M {
BIOS {
EC 128K
RW_MRC_CACHE 64K
FMAP 4K
COREBOOT(CBFS)
}
}

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src/mainboard/amd/bilby/board_info.txt Normal file
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Category: eval

24
src/mainboard/amd/bilby/bootblock.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <amdblocks/lpc.h>
#include <superio/smsc/sio1036/sio1036.h>
#include "gpio.h"
#define SERIAL_DEV PNP_DEV(CONFIG_SUPERIO_ADDR_BASE, SIO1036_SP1)
void bootblock_mainboard_early_init(void)
{
mainboard_program_early_gpios();
if (CONFIG(SUPERIO_SMSC_SIO1036)) {
if (CONFIG_SUPERIO_ADDR_BASE == 0x4e) {
lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F);
} else {
// set up 16 byte wide I/O range window for the super IO
lpc_set_wideio_range(CONFIG_SUPERIO_ADDR_BASE & ~0xF, 16);
}
lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE);
sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
}

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src/mainboard/amd/bilby/devicetree.cb Normal file
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# SPDX-License-Identifier: GPL-2.0-only
chip soc/amd/picasso
register "acp_pin_cfg" = "I2S_PINS_MAX_HDA"
# Set FADT Configuration
register "common_config.fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042"
register "common_config.fadt_flags" = "ACPI_FADT_SLEEP_BUTTON" # See table 5-34 ACPI 6.3 spec
register "emmc_config" = "{
.timing = SD_EMMC_DISABLE,
}"
register "has_usb2_phy_tune_params" = "1"
# Controller0 Port0 Default
register "usb_2_port_tune_params[0]" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller0 Port1 Default
register "usb_2_port_tune_params[1]" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller0 Port2 Default
register "usb_2_port_tune_params[2]" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller0 Port3 Default
register "usb_2_port_tune_params[3]" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0x6,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller0 Port4 Default
register "usb_2_port_tune_params[4]" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# Controller0 Port5 Default
register "usb_2_port_tune_params[5]" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x02,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.tx_vref_tune = 0x5,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# USB OC pin mapping; all ports share one OC pin
register "usb_port_overcurrent_pin[0]" = "USB_OC_PIN_0"
register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0"
register "usb_port_overcurrent_pin[2]" = "USB_OC_PIN_0"
register "usb_port_overcurrent_pin[3]" = "USB_OC_PIN_0"
register "usb_port_overcurrent_pin[4]" = "USB_OC_PIN_0"
register "usb_port_overcurrent_pin[5]" = "USB_OC_PIN_0"
# SPI Configuration
register "common_config.spi_config" = "{
.normal_speed = SPI_SPEED_33M, /* MHz */
.fast_speed = SPI_SPEED_66M, /* MHz */
.altio_speed = SPI_SPEED_33M, /* MHz */
.tpm_speed = SPI_SPEED_33M, /* MHz */
.read_mode = SPI_READ_MODE_QUAD114,
}"
# eSPI Configuration
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN,
.generic_io_range[0] = {
.base = 0x662,
.size = 8,
},
.io_mode = ESPI_IO_MODE_SINGLE,
.op_freq_mhz = ESPI_OP_FREQ_33_MHZ,
.crc_check_enable = 1,
.dedicated_alert_pin = 1,
.periph_ch_en = 0,
.vw_ch_en = 0,
.oob_ch_en = 0,
.flash_ch_en = 0,
}"
# genral purpose PCIe clock output configuration
register "gpp_clk_config[0]" = "GPP_CLK_REQ"
register "gpp_clk_config[1]" = "GPP_CLK_REQ"
register "gpp_clk_config[2]" = "GPP_CLK_REQ"
register "gpp_clk_config[3]" = "GPP_CLK_OFF"
register "gpp_clk_config[4]" = "GPP_CLK_REQ"
register "gpp_clk_config[5]" = "GPP_CLK_OFF"
register "gpp_clk_config[6]" = "GPP_CLK_OFF"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
subsystemid 0x1022 0x1510 inherit
device pci 0.0 on end # Root Complex
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Dummy Host Bridge
device pci 1.1 on end # Bridge to PCIe Ethernet chip
device pci 8.0 on end # Dummy Host Bridge
device pci 8.1 on # Bridge to Bus A
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
device pci 0.3 on end # USB 3.1
device pci 0.4 off end # USB 3.1
device pci 0.5 on end # Audio
device pci 0.6 on end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
device pci 8.2 on # Bridge to Bus B
device pci 0.0 off end # AHCI
device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC
end
device pci 14.0 on end # SMBus
device pci 14.3 on # D14F3 bridge
chip superio/smsc/sio1036 # optional debug card
end
end
device pci 14.6 off end # SDHCI
device pci 18.0 on end # Data fabric [0-7]
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
device pci 18.4 on end
device pci 18.5 on end
device pci 18.6 on end
device pci 18.7 on end
end # domain
device mmio 0xfedc9000 on end # UART0
device mmio 0xfedca000 on end # UART1
device mmio 0xfedce000 off end # UART2
device mmio 0xfedcf000 off end # UART3
end # chip soc/amd/picasso

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src/mainboard/amd/bilby/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#define MAINBOARD_HAS_SPEAKER 1
/* DefinitionBlock Statement */
#include <acpi/acpi.h>
DefinitionBlock (
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x00010001 /* OEM Revision */
)
{ /* Start of ASL file */
#include <acpi/dsdt_top.asl>
/* global NVS and variables */
#include <globalnvs.asl>
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
/* Describe the processor tree (\_PR) */
#include <cpu.asl>
/* Contains the supported sleep states for this chipset */
#include <sleepstates.asl>
/* Contains _SWS methods */
#include <soc/amd/common/acpi/acpi_wake_source.asl>
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* Describe the SOC */
#include <soc.asl>
} /* End \_SB scope */
}
/* End of ASL file */

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src/mainboard/amd/bilby/early_gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
#include "gpio.h"
/* GPIO pins used by coreboot should be initialized in bootblock */
static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* not LLB */
PAD_GPI(GPIO_12, PULL_UP),
/* not USB_OC1_L */
PAD_GPI(GPIO_17, PULL_UP),
/* not USB_OC2_L */
PAD_GPI(GPIO_18, PULL_UP),
/* SDIO eMMC power control */
PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE),
/* PCIe Reset 0 */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* PCIe Reset 1 */
PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
/* eSPI CS# */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* FANOUT0 */
PAD_NF(GPIO_85, FANOUT0, PULL_NONE),
/* PC beep to codec */
PAD_NF(GPIO_91, SPKR, PULL_NONE),
};
void mainboard_program_early_gpios(void)
{
program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
}

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src/mainboard/amd/bilby/emmc_gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
#include "gpio.h"
/* eMMC controller driving either an SD card or eMMC device. */
static const struct soc_amd_gpio emmc_gpios[] = {
PAD_NF(GPIO_21, EMMC_CMD, PULL_UP),
PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_UP),
PAD_NF(GPIO_68, EMMC_CD, PULL_UP),
PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE),
PAD_NF(GPIO_104, EMMC_DATA0, PULL_UP),
PAD_NF(GPIO_105, EMMC_DATA1, PULL_UP),
PAD_NF(GPIO_106, EMMC_DATA2, PULL_UP),
PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE),
PAD_NF(GPIO_74, EMMC_DATA4, PULL_UP),
PAD_NF(GPIO_75, EMMC_DATA6, PULL_UP),
PAD_NF(GPIO_87, EMMC_DATA7, PULL_UP),
PAD_NF(GPIO_88, EMMC_DATA5, PULL_UP),
PAD_NF(GPIO_109, EMMC_DS, PULL_UP),
};
/* Don't call this if the board uses the LPC bus. */
void mainboard_program_emmc_gpios(void)
{
program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios));
}

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src/mainboard/amd/bilby/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/gpio.h>
#include "gpio.h"
/*
* As a rule of thumb, GPIO pins used by coreboot should be initialized at
* bootblock while GPIO pins used only by the OS should be initialized at
* ramstage.
*/
static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* EC SCI# */
PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW),
/* I2S SDIN */
PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE),
/* I2S LRCLK */
PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE),
/* not Blink */
PAD_GPI(GPIO_11, PULL_UP),
/* APU_ALS_INT# */
PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
/* SD card detect */
PAD_GPI(GPIO_31, PULL_UP),
/* NFC IRQ */
PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS),
/* NFC wake output# */
PAD_GPO(GPIO_89, HIGH),
};
void mainboard_program_gpios(void)
{
program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram));
}

10
src/mainboard/amd/bilby/gpio.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */
void mainboard_program_gpios(void); /* ramstage GPIO configuration */
void mainboard_program_emmc_gpios(void); /* ramstage eMMC pin mux configuration */
#endif /* MAINBOARD_GPIO_H */

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src/mainboard/amd/bilby/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* Realtek ALC701 on mainboard */
0x10ec0701,
0x00000000,
0x00000016,
AZALIA_SUBVENDOR(0, 0x1022D001), // HDA Codec Subsystem ID: 0x1022D001
AZALIA_RESET(1), // Widget node 0x01 :
AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), // Pin widget 0x12 - DMIC
AZALIA_PIN_CFG(0, 0x13, 0x40000000), // Pin widget 0x13 - DMIC
AZALIA_PIN_CFG(0, 0x14, 0x90170110), // Pin widget 0x14 - FRONT (Port-D)
AZALIA_PIN_CFG(0, 0x15, 0x411111f0), // Pin widget 0x15 - I2S-OUT
AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // Pin widget 0x16 - LINE3 (Port-B)
AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // Pin widget 0x17 - I2S-OUT
AZALIA_PIN_CFG(0, 0x18, 0x411111f0), // Pin widget 0x18 - I2S-IN
AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // Pin widget 0x19 - MIC2 (Port-F)
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // Pin widget 0x1A - LINE1 (Port-C)
AZALIA_PIN_CFG(0, 0x1b, 0x04a11050), // Pin widget 0x1B - LINE2 (Port-E)
AZALIA_PIN_CFG(0, 0x1d, 0x40600001), // Pin widget 0x1D - PC-BEEP
AZALIA_PIN_CFG(0, 0x1e, 0x04451130), // Pin widget 0x1E - S/PDIF-OUT
AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), // Pin widget 0x1F - S/PDIF-IN
AZALIA_PIN_CFG(0, 0x21, 0x04211020), // Pin widget 0x21 - HP-OUT (Port-I)
AZALIA_PIN_CFG(0, 0x29, 0x411111f0), // Pin widget 0x29 - I2S-IN
0x02050038, 0x02047901, 0x0205006b, 0x02040260, // NID 0x20 -0 Set Class-D output
// power as 2.2W@4 Ohm, and
// MIC2-VREFO-R is controlled by
// Line2 port.
0x0205001a, 0x02048c03, 0x02050045, 0x0204b289, // NID 0x20 - 1
0x0205004a, 0x0204201b, 0x0205004a, 0x0204201b, // NID 0x20 - 2
0x02050010, 0x02040420, 0x01470c00, 0x02050036, // Dos beep path - 1
0x02047151, 0x01470740, 0x0143b000, 0x01470c02, // Dos beep path - 2
/* Realtek ALC285 on extension card */
0x10ec0285,
0x00000000,
0x00000028,
AZALIA_SUBVENDOR(0, 0x1022D002),
AZALIA_RESET(1), // Widget node 0x01 :
AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), // Pin widget 0x12 - DMIC
AZALIA_PIN_CFG(0, 0x13, 0x40000000), // Pin widget 0x13 - DMIC
AZALIA_PIN_CFG(0, 0x14, 0x90170110), // Pin widget 0x14 - Front (Port-D)
AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // Pin widget 0x16 - NPC
AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // Pin widget 0x17 - I2S OUT
AZALIA_PIN_CFG(0, 0x18, 0x411111f0), // Pin widget 0x18 - I2S IN
AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // Pin widget 0x19 - MIC2 (Port-F)
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // Pin widget 0x1A - NPC
AZALIA_PIN_CFG(0, 0x1b, 0x04a19030), // Pin widget 0x1B - LINE2 (Port-E)
AZALIA_PIN_CFG(0, 0x1d, 0x4066192d), // Pin widget 0x1D - BEEP-IN
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), // Pin widget 0x1E - S/PDIF-OUT
AZALIA_PIN_CFG(0, 0x21, 0x04211020), // Pin widget 0x21 - HP1-OUT (Port-I)
0x05c50011, 0x05c40003, 0x05c50011, 0x05c40003, // dis. Silence detect delay turn off
0x0205003c, 0x0204f254, 0x0205003c, 0x0204f214, // Class-D power on reset
0x02050045, 0x0204b009, 0x02050063, 0x02040020, // Set TRS + turn off MIC2 VREFO
// gating with HP-JD.
0x0205004a, 0x020420b0, 0x02050009, 0x02043803, // Enable HP JD + Set JD2 to 1 port
// JD for WoV
0x0205000b, 0x0204777a, 0x0205000b, 0x0204777a, // Set TRS + Set JD2 pull up.
0x02050038, 0x02043909, 0x05c50000, 0x05c43482, // NID 0x20 set class-D to 2W@4ohm
// (+12dB gain) + Set sine
// tone gain(0x34)
0x05350000, 0x0534002a, 0x05350000, 0x0534002a, // Disable EQ + set 100Hz 2nd High
// Pass filter
0x0535001d, 0x05340800, 0x0535001e, 0x05340800, // Left Channel-1
0x05350005, 0x053403f6, 0x05350006, 0x0534854c, // Left Channel-2
0x05350007, 0x05341e09, 0x05350008, 0x05346472, // Left Channel-3
0x05350009, 0x053401fb, 0x0535000a, 0x05344836, // Left Channel-4
0x0535000b, 0x05341c00, 0x0535000c, 0x05340000, // Left Channel-5
0x0535000d, 0x05340200, 0x0535000e, 0x05340000, // Left Channel-6
0x05450000, 0x05440000, 0x0545001d, 0x05440800, // Right Channel-1
0x0545001e, 0x05440800, 0x05450005, 0x054403f6, // Right Channel-2
0x05450006, 0x0544854c, 0x05450007, 0x05441e09, // Right Channel-3
0x05450008, 0x05446472, 0x05450009, 0x054401fb, // Right Channel-4
0x0545000a, 0x05444836, 0x0545000b, 0x05441c00, // Right Channel-5
0x0545000c, 0x05440000, 0x0545000d, 0x05440200, // Right Channel-6
0x0545000e, 0x05440000, 0x05350000, 0x0534c02a, // Right Channel-7+ EQ Update & Enable
0x05d50006, 0x05d44c50, 0x05d50002, 0x05d46004, // AGC-1 Disable + (Front Gain=0dB )
0x05d50003, 0x05d45e5e, 0x05d50001, 0x05d4d783, // AGC-2 (Back Boost Gain = -0.375dB,
// Limiter = -1.125dB)
0x05d50009, 0x05d451ff, 0x05d50006, 0x05d44e50, // AGC-3 + AGC Enable
0x02050010, 0x02040020, 0x02050040, 0x02048800, // EAPD set to verb-control.
0x02050030, 0x02049000, 0x02050037, 0x0204fe15, // Class D silent detection Enable
// -84dB threshold
0x05b50006, 0x05b40044, 0x05a50001, 0x05a4001f, // Set headphone gain and Set pin1
// to GPIO2
};
const u32 pc_beep_verbs[] = {
};
AZALIA_ARRAY_SIZES;

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <device/device.h>
#include <acpi/acpi.h>
#include <amdblocks/amd_pci_util.h>
#include <FspsUpd.h>
#include <soc/cpu.h>
#include <soc/southbridge.h>
#include <soc/pci_devs.h>
#include <types.h>
#include <commonlib/helpers.h>
#include <chip.h>
#include "gpio.h"
/* TODO: recheck IRQ tables */
/*
* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
* This table is responsible for physically routing the PIC and
* IOAPIC IRQs to the different PCI devices on the system. It
* is read and written via registers 0xC00/0xC01 as an
* Index/Data pair. These values are chipset and mainboard
* dependent and should be updated accordingly.
*/
static uint8_t fch_pic_routing[0x80];
static uint8_t fch_apic_routing[0x80];
_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
"PIC and APIC FCH interrupt tables must be the same size");
static const struct fch_irq_routing {
uint8_t intr_index;
uint8_t pic_irq_num;
uint8_t apic_irq_num;
} bilby_fch[] = {
{ PIRQ_A, 8, 16 },
{ PIRQ_B, 10, 17 },
{ PIRQ_C, 11, 18 },
{ PIRQ_D, 12, 19 },
{ PIRQ_SCI, 9, 9 },
{ PIRQ_SD, PIRQ_NC, 16 },
{ PIRQ_SDIO, PIRQ_NC, 16 },
{ PIRQ_SATA, PIRQ_NC, 19 },
{ PIRQ_EMMC, PIRQ_NC, 17 },
{ PIRQ_GPIO, 7, 7 },
{ PIRQ_I2C2, 6, 6 },
{ PIRQ_I2C3, 14, 14 },
{ PIRQ_UART0, 4, 4 },
{ PIRQ_UART1, 3, 3 },
{ PIRQ_UART2, 4, 4 },
{ PIRQ_UART3, 3, 3 },
/* The MISC registers are not interrupt numbers */
{ PIRQ_MISC, 0xfa, 0x00 },
{ PIRQ_MISC0, 0x91, 0x00 },
{ PIRQ_MISC1, 0x00, 0x00 },
{ PIRQ_MISC2, 0x00, 0x00 },
};
static void init_tables(void)
{
const struct fch_irq_routing *entry;
int i;
memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
for (i = 0; i < ARRAY_SIZE(bilby_fch); i++) {
entry = bilby_fch + i;
fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
}
}
static void pirq_setup(void)
{
init_tables();
intr_data_ptr = fch_apic_routing;
picr_data_ptr = fch_pic_routing;
}
static void mainboard_init(void *chip_info)
{
struct soc_amd_picasso_config *cfg = config_of_soc();
if (!CONFIG(BILBY_LPC))
cfg->emmc_config.timing = SD_EMMC_EMMC_HS400;
mainboard_program_gpios();
/* Re-muxing LPCCLK0 can hang the system if LPC is in use. */
if (CONFIG(BILBY_LPC))
printk(BIOS_INFO, "eMMC not available due to LPC requirement\n");
else
mainboard_program_emmc_gpios();
}
static void bilby_enable(struct device *dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = bilby_enable,
};

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/platform_descriptors.h>
#include <types.h>
static const fsp_dxio_descriptor pollock_dxio_descriptors[] = {
{ /* NVME SSD */
.port_present = true,
.engine_type = PCIE_ENGINE,
.start_logical_lane = 0,
.end_logical_lane = 0,
.device_number = 1,
.function_number = 3,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ0
},
{ /* WWAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
.start_logical_lane = 1,
.end_logical_lane = 1,
.device_number = 1,
.function_number = 4,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ2
},
{ /* LAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
.start_logical_lane = 4,
.end_logical_lane = 4,
.device_number = 1,
.function_number = 1,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ1
},
{ /* WLAN */
.port_present = true,
.engine_type = PCIE_ENGINE,
.start_logical_lane = 5,
.end_logical_lane = 5,
.device_number = 1,
.function_number = 2,
.link_aspm = ASPM_L1,
.link_aspm_L1_1 = true,
.link_aspm_L1_2 = true,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ4
}
};
fsp_ddi_descriptor pollock_ddi_descriptors[] = {
{ /* DDI0 - eDP */
.connector_type = EDP,
.aux_index = AUX1,
.hdp_index = HDP1
},
{ /* DDI1 - DP */
.connector_type = DP,
.aux_index = AUX2,
.hdp_index = HDP2
},
{ /* DDI2 - DP */
.connector_type = DP,
.aux_index = AUX4,
.hdp_index = HDP4,
}
};
void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
*dxio_descs = pollock_dxio_descriptors;
*dxio_num = ARRAY_SIZE(pollock_dxio_descriptors);
*ddi_descs = pollock_ddi_descriptors;
*ddi_num = ARRAY_SIZE(pollock_ddi_descriptors);
}

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/* SPDX-License-Identifier: GPL-2.0-only */