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mainboard/bifferos: remove bifferboard 

This board can't be found to be tested, and compiles romstage with
romcc.  If desired, it can be continued in the 4.6 branch.

Change-Id: I4826c277bbb444c2f0573729d76cd492ade95b4c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Martin Roth 2017-06-18 13:18:10 -06:00
parent be05f5d7d1
commit 287f9638af
7 changed files with 0 additions and 116 deletions
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31
src/mainboard/bifferos/Kconfig
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@ -1,31 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if VENDOR_BIFFEROS
choice
prompt "Mainboard model"
source "src/mainboard/bifferos/*/Kconfig.name"
endchoice
source "src/mainboard/bifferos/*/Kconfig"
config MAINBOARD_VENDOR
string
default "Bifferos"
endif # VENDOR_BIFFEROS

2
src/mainboard/bifferos/Kconfig.name
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config VENDOR_BIFFEROS
bool "Bifferos"

16
src/mainboard/bifferos/bifferboard/Kconfig
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if BOARD_BIFFEROS_BIFFERBOARD
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_128
select SOC_RDC_R8610
config MAINBOARD_DIR
string
default bifferos/bifferboard
config MAINBOARD_PART_NUMBER
string
default "Bifferboard"
endif # BOARD_BIFFEROS_BIFFERBOARD

2
src/mainboard/bifferos/bifferboard/Kconfig.name
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config BOARD_BIFFEROS_BIFFERBOARD
bool "Bifferboard"

1
src/mainboard/bifferos/bifferboard/board_info.txt
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Category: half

6
src/mainboard/bifferos/bifferboard/devicetree.cb
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chip soc/rdc/r8610
device domain 0 on
device pci 0.0 on end
device pci 7.0 on end # SB
end
end

58
src/mainboard/bifferos/bifferboard/romstage.c
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <pc80/mc146818rtc.h>
#include "arch/x86/romcc_console.c"
#include <console/console.h>
#include <cpu/x86/cache.h>
static void main(void)
{
uint32_t tmp;
post_code(0x05);
/* Set timer1 to pulse generator 15us for memory refresh */
outb(0x54, 0x43);
outb(0x12, 0x41);
/* CPU setup, romcc pukes on invd() */
asm volatile ("invd");
enable_cache();
/* Set serial base */
pci_write_config32(PCI_DEV(0,7,0), 0x54, 0x3f8);
/* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
pci_write_config32(PCI_DEV(0,7,0), 0x50, 0x84101012);
console_init();
/* memory init */
pci_write_config32(PCI_DEV(0,0,0), 0x68, 0x6c99f);
pci_write_config32(PCI_DEV(0,0,0), 0x6c, 0x800451);
pci_write_config32(PCI_DEV(0,0,0), 0x70, 0x4000003);
/* memory phase/buffer strength for read and writes */
tmp = pci_read_config32(PCI_DEV(0,0,0), 0x64);
tmp &= 0x0FF00FFFF;
tmp |= 0x790000;
pci_write_config32(PCI_DEV(0,0,0), 0x64, tmp);
/* Route Cseg, Dseg, Eseg and Fseg to RAM */
pci_write_config32(PCI_DEV(0,0,0), 0x84, 0x3ffffff0);
}