mainboard/bifferos: remove bifferboard
This board can't be found to be tested, and compiles romstage with romcc. If desired, it can be continued in the 4.6 branch. Change-Id: I4826c277bbb444c2f0573729d76cd492ade95b4c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Martin Roth
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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if VENDOR_BIFFEROS
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choice
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prompt "Mainboard model"
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source "src/mainboard/bifferos/*/Kconfig.name"
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endchoice
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source "src/mainboard/bifferos/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "Bifferos"
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endif # VENDOR_BIFFEROS
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config VENDOR_BIFFEROS
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bool "Bifferos"
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if BOARD_BIFFEROS_BIFFERBOARD
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_128
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select SOC_RDC_R8610
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config MAINBOARD_DIR
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string
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default bifferos/bifferboard
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config MAINBOARD_PART_NUMBER
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string
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default "Bifferboard"
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endif # BOARD_BIFFEROS_BIFFERBOARD
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config BOARD_BIFFEROS_BIFFERBOARD
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bool "Bifferboard"
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Category: half
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chip soc/rdc/r8610
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device domain 0 on
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device pci 0.0 on end
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device pci 7.0 on end # SB
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end
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end
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <pc80/mc146818rtc.h>
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#include "arch/x86/romcc_console.c"
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#include <console/console.h>
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#include <cpu/x86/cache.h>
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static void main(void)
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{
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uint32_t tmp;
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post_code(0x05);
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/* Set timer1 to pulse generator 15us for memory refresh */
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outb(0x54, 0x43);
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outb(0x12, 0x41);
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/* CPU setup, romcc pukes on invd() */
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asm volatile ("invd");
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enable_cache();
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/* Set serial base */
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pci_write_config32(PCI_DEV(0,7,0), 0x54, 0x3f8);
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/* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
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pci_write_config32(PCI_DEV(0,7,0), 0x50, 0x84101012);
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console_init();
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/* memory init */
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pci_write_config32(PCI_DEV(0,0,0), 0x68, 0x6c99f);
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pci_write_config32(PCI_DEV(0,0,0), 0x6c, 0x800451);
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pci_write_config32(PCI_DEV(0,0,0), 0x70, 0x4000003);
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/* memory phase/buffer strength for read and writes */
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tmp = pci_read_config32(PCI_DEV(0,0,0), 0x64);
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tmp &= 0x0FF00FFFF;
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tmp |= 0x790000;
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pci_write_config32(PCI_DEV(0,0,0), 0x64, tmp);
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/* Route Cseg, Dseg, Eseg and Fseg to RAM */
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pci_write_config32(PCI_DEV(0,0,0), 0x84, 0x3ffffff0);
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}
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