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Add CONFIG_VGA_ROM_RUN to dbm690t and pistachio, otherwise the 

VGA ROM can not run. After make, run
> ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom   pci1002,791f.rom  optionrom
to make the final image with vga bios.

The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should
be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I
cant make test on.

##    Index: src/southbridge/amd/rs690/chip.h
##    ===================================================================
##    --- src/southbridge/amd/rs690/chip.h	(revision 4782)
##    +++ src/southbridge/amd/rs690/chip.h	(working copy)
##    @@ -23,7 +23,6 @@
##     /* Member variables are defined in Config.lb. */
##     struct southbridge_amd_rs690_config
##     {
##    -	u32 vga_rom_address;		/* The location that the VGA rom has been appened. */
##     	u8 gpp_configuration;	/* The configuration of General Purpose Port, A/B/C/D/E. */
##     	u8 port_enable;		/* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
##     	u8 gfx_dev2_dev3;	/* for GFX Core initialization REFCLK_SEL */
##

Don't apply above patch about rs690/chip.h before every board has been fixed.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2009-10-16 07:44:04 +00:00 committed by Zheng Bao
parent 9d37532bc1
commit 289a2f5aad
9 changed files with 10 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/dbm690t/Config.lb
View File

@ -136,7 +136,6 @@ config chip.h
#The variables belong to mainboard are defined here.
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -170,7 +169,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

4
src/mainboard/amd/dbm690t/Options.lb
View File

@ -73,6 +73,7 @@ uses HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VGA_ROM_RUN
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
@ -103,8 +104,6 @@ default CONFIG_ROM_SIZE=524288
##
## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
#default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
#256K
default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
##
@ -160,6 +159,7 @@ default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
default CONFIG_VGA_ROM_RUN=1
# BTDC: Only one HT device on Herring.
#HT Unit ID offset

2
src/mainboard/amd/dbm690t/devicetree.cb
View File

@ -1,5 +1,4 @@
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -33,7 +32,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

2
src/mainboard/amd/pistachio/Config.lb
View File

@ -136,7 +136,6 @@ config chip.h
#The variables belong to mainboard are defined here.
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -171,7 +170,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

2
src/mainboard/amd/pistachio/Options.lb
View File

@ -73,6 +73,7 @@ uses HOSTCC
uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses CONFIG_VGA_ROM_RUN
uses CONFIG_HW_MEM_HOLE_SIZEK
uses CONFIG_HT_CHAIN_UNITID_BASE
uses CONFIG_HT_CHAIN_END_UNITID_BASE
@ -158,6 +159,7 @@ default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
default CONFIG_VGA_ROM_RUN=1
# BTDC: Only one HT device on Herring.
#HT Unit ID offset

2
src/mainboard/amd/pistachio/devicetree.cb
View File

@ -1,5 +1,4 @@
#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
#Define vga_rom_address = 0xfff0000
#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
# 1: the system allows a PCIE link to be established on Dev2 or Dev3.
@ -34,7 +33,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 6.0 on end # PCIE P2P bridge 0x7916
device pci 7.0 on end # PCIE P2P bridge 0x7917
device pci 8.0 off end # NB/SB Link P2P bridge
register "vga_rom_address" = "0xfff00000"
register "gpp_configuration" = "4"
register "port_enable" = "0xfc"
register "gfx_dev2_dev3" = "1"

8
src/southbridge/amd/rs690/rs690_gfx.c
View File

@ -77,13 +77,9 @@ static void internal_gfx_pci_dev_init(struct device *dev)
(struct southbridge_amd_rs690_config *)dev->chip_info;
deviceid = pci_read_config16(dev, PCI_DEVICE_ID);
vendorid = pci_read_config16(dev, PCI_VENDOR_ID);
printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x, vga_rom_address=0x%x.\n",
deviceid, vendorid, cfg->vga_rom_address);
printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n",
deviceid, vendorid);
#if 0 /* I think these should be done in Config.lb. Please check it. */
dev->on_mainboard = 1;
dev->rom_address = cfg->vga_rom_address; /* 0xfff00000; */
#endif
pci_dev_init(dev);
/* clk ind */

4
targets/amd/dbm690t/Config.lb
View File

@ -4,14 +4,14 @@ target dbm690t
mainboard amd/dbm690t
romimage "normal"
option CONFIG_ROM_SIZE = 1024*1024 - 55808
option CONFIG_ROM_SIZE = 1024*1024
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
payload ../payload.elf
end
romimage "fallback"
romimage "fallback"
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000

4
targets/amd/pistachio/Config.lb
View File

@ -4,14 +4,14 @@ target pistachio
mainboard amd/pistachio
romimage "normal"
option CONFIG_ROM_SIZE = 1024*1024 - 55808
option CONFIG_ROM_SIZE = 1024*1024
option CONFIG_USE_FALLBACK_IMAGE=0
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000
payload ../payload.elf
end
romimage "fallback"
romimage "fallback"
option CONFIG_USE_FALLBACK_IMAGE=1
option CONFIG_ROM_IMAGE_SIZE=0x20000
option CONFIG_XIP_ROM_SIZE=0x20000