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soc/amd/*/cpu: handle mp_init_with_smm failure 

When the mp_init_with_smm call returns a failure, coreboot can't just
continue with the initialization and boot process due to the system
being in a bad state. Ignoring the failure here would just cause the
boot process failing elsewhere where it may not be obvious that the
failed multi-processor initialization step was the root cause of that.
I'm not 100% sure if calling do_cold_reset or calling die_with_post_code
is the better option here. Calling do_cold_reset likely here would
likely result in a boot-failure loop, so I call die_with_post_code here.

BUG=b:193809448

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-11-02 17:15:58 +01:00
parent c435038c55
commit 28a0a14b5b
3 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/amd/cezanne/cpu.c
View File

@ -51,9 +51,9 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus) void mp_init_cpus(struct bus *cpu_bus)
{ {
/* Clear for take-off */ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
/* TODO: Handle mp_init_with_smm failure? */ die_with_post_code(POST_HW_INIT_FAILURE,
mp_init_with_smm(cpu_bus, &mp_ops); "mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);

6
src/soc/amd/picasso/cpu.c
View File

@ -55,9 +55,9 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus) void mp_init_cpus(struct bus *cpu_bus)
{ {
/* Clear for take-off */ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
/* TODO: Handle mp_init_with_smm failure? */ die_with_post_code(POST_HW_INIT_FAILURE,
mp_init_with_smm(cpu_bus, &mp_ops); "mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);

6
src/soc/amd/stoneyridge/cpu.c
View File

@ -52,9 +52,9 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus) void mp_init_cpus(struct bus *cpu_bus)
{ {
/* Clear for take-off */ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
/* TODO: Handle mp_init_with_smm failure? */ die_with_post_code(POST_HW_INIT_FAILURE,
mp_init_with_smm(cpu_bus, &mp_ops); "mp_init_with_smm failed. Halting.\n");
/* The flash is now no longer cacheable. Reset to WP for performance. */ /* The flash is now no longer cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);