soc/ucb/riscv: select BOOTBLOCK_CONSOLE

Change-Id: I847d7686dec04e9fae7db13d53adc8ca32c56f3a
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16158
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer 2016-08-11 22:49:14 +02:00 committed by Ronald G. Minnich
parent 12974436a9
commit 28a3ee6d29
1 changed files with 1 additions and 0 deletions

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@ -4,6 +4,7 @@ config SOC_UCB_RISCV
select ARCH_VERSTAGE_RISCV select ARCH_VERSTAGE_RISCV
select ARCH_ROMSTAGE_RISCV select ARCH_ROMSTAGE_RISCV
select ARCH_RAMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV
select BOOTBLOCK_CONSOLE
bool bool
default n default n