Supermicro H8SCM: Use SPD read code from F15 wrapper
Changes: - Get rid of the h8scm mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2777/ AMD Fam15: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I575221039ad65a59ae0f93397ef1038b669e81c7 Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com> Reviewed-on: http://review.coreboot.org/2829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kimarie Hoot
Stefan Reinauer
parent
2a9145e743
commit
28b99c05a1
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@ -23,6 +23,7 @@
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#include "Ids.h"
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#include "Ids.h"
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#include "OptionsIds.h"
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#include "OptionsIds.h"
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#include "heapManager.h"
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#include "heapManager.h"
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#include <northbridge/amd/agesa/family15/dimmSpd.h>
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STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
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STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
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{
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{
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@ -81,8 +82,6 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
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},
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},
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};
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};
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extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
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AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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{
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UINTN i;
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UINTN i;
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@ -487,7 +486,11 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
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{
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{
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AGESA_STATUS Status;
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AGESA_STATUS Status;
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Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
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#ifdef __PRE_RAM__
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Status = agesa_ReadSPD (Func, Data, ConfigPtr);
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#else
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Status = AGESA_UNSUPPORTED;
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#endif
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return Status;
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return Status;
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}
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}
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@ -22,7 +22,6 @@ romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
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romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
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romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
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romstage-y += buildOpts.c
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romstage-y += buildOpts.c
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romstage-y += agesawrapper.c
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romstage-y += agesawrapper.c
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romstage-y += dimmSpd.c
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romstage-y += BiosCallOuts.c
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romstage-y += BiosCallOuts.c
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romstage-y += platform_oem.c
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romstage-y += platform_oem.c
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@ -31,7 +30,6 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
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ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
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ramstage-y += buildOpts.c
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ramstage-y += buildOpts.c
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ramstage-y += agesawrapper.c
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ramstage-y += agesawrapper.c
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ramstage-y += dimmSpd.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += platform_oem.c
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ramstage-y += platform_oem.c
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@ -121,6 +121,12 @@ chip northbridge/amd/agesa/family15/root_complex
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device pci 18.3 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.4 on end
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device pci 18.5 on end #f15
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device pci 18.5 on end #f15
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register "spdAddrLookup" = "
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{
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{ {0xA4, 0xA6}, {0xA0, 0xA2}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 0
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{ {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 (unused)
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}"
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end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
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end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
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end #domain
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end #domain
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end #northbridge/amd/agesa/family15/root_complex
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end #northbridge/amd/agesa/family15/root_complex
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@ -1,229 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "Porting.h"
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#include "AGESA.h"
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#include "amdlib.h"
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <device/pci_ids.h>
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AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
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#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
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/* SP5100 GPIO 49-52 contoled by SMBUS PCI_Reg 0x52 */
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#define SP5100_GPIO37_46_47_48 0xA6
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#define SP5100_GPIO49_52 0x50
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/**
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* TODO not support all GPIO yet
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* @param reg -GPIO Cntrl Register
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* @param out -GPIO bitmap
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* @param out -GPIO enable bitmap
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* @return old setting
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*/
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static u8 sp5100_set_gpio(u8 reg, u8 out, u8 enable)
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{
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u8 value, ret;
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device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
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value = pci_read_config8(sm_dev, reg);
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ret = value;
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value &= ~(enable);
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value |= out;
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value &= ~(enable << 4);
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pci_write_config8(sm_dev, reg, value);
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return ret;
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}
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static void sp5100_restore_gpio(u8 reg, u8 value)
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{
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device_t sm_dev = PCI_DEV(0, 0x14, 0);
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pci_write_config8(sm_dev, reg, value);
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}
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/*-----------------------------------------------------------------------------
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*
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* SPD address table - porting required
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*/
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static const UINT8 spdAddressLookup [1] [2] [2] = { // socket, channel, dimm
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/* socket 0 */
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{
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{0xA4, 0xA6},
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{0xA0, 0xA2},
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},
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/* socket 1 */
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/* { */
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/* {0xA0, 0xA4, 0xA8}, */
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/* {0xA2, 0xA6, 0xAA}, */
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/* }, */
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};
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/*-----------------------------------------------------------------------------
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*
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* readSmbusByteData - read a single SPD byte from any offset
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*/
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static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
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{
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unsigned int status;
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UINT64 limit;
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address |= 1; // set read bit
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outb(0xFF, iobase + 0); // clear error status
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outb(0x1F, iobase + 1); // clear error status
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outb(offset, iobase + 3); // offset in eeprom
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outb(address, iobase + 4); // slave address and read bit
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outb(0x48, iobase + 2); // read byte command
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// time limit to avoid hanging for unexpected error status (should never happen)
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limit = __rdtsc () + 2000000000 / 10;
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for (;;)
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{
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status = inb(iobase);
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if (__rdtsc () > limit) break;
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if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
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if ((status & 1) == 1) continue; // HostBusy set, keep waiting
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break;
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}
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buffer [0] = inb(iobase + 5);
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if (status == 2) status = 0; // check for done with no errors
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return status;
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}
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/*-----------------------------------------------------------------------------
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*
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* readSmbusByte - read a single SPD byte from the default offset
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* this function is faster function readSmbusByteData
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*/
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static int readSmbusByte (int iobase, int address, char *buffer)
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{
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unsigned int status;
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UINT64 limit;
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outb(0xFF, iobase + 0); // clear error status
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outb(0x44, iobase + 2); // read command
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// time limit to avoid hanging for unexpected error status
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limit = __rdtsc () + 2000000000 / 10;
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for (;;)
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{
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status = inb(iobase);
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if (__rdtsc () > limit) break;
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if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting
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if ((status & 1) == 1) continue; // HostBusy set, keep waiting
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break;
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}
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buffer [0] = inb(iobase + 5);
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if (status == 2) status = 0; // check for done with no errors
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return status;
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}
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/*---------------------------------------------------------------------------
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*
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* readspd - Read one or more SPD bytes from a DIMM.
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* Start with offset zero and read sequentially.
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* Optimization relies on autoincrement to avoid
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* sending offset for every byte.
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* Reads 128 bytes in 7-8 ms at 400 KHz.
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*/
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static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
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{
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int index, error;
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/* read the first byte using offset zero */
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error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
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if (error) {
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return error;
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}
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/* read the remaining bytes using auto-increment for speed */
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for (index = 1; index < count; index++)
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{
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error = readSmbusByte (iobase, SmbusSlaveAddress, buffer + index);
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if (error)
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return error;
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}
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return 0;
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}
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static void setupFch (int ioBase)
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{
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outb(66000000 / 400000 / 4, ioBase + 0x0E); /* set SMBus clock to 400 KHz */
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}
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AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
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{
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AGESA_STATUS status;
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int spdAddress, ioBase, i;
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u8 i2c_channel;
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u8 backup;
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device_t sm_dev;
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if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
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if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
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if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
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i2c_channel = (UINT8) info->SocketId;
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printk(BIOS_DEBUG, "S=%x, c=%x, d=%x\n", info->SocketId, info->MemChannelId, info->DimmId);
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/* set IDTQS3253 i2c channel
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* GPIO49,48 control the S1,S0
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* S1 S0 true table
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* 0 0 channel 0
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* 0 1 channel 1
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* 1 0 channel 2 - Socket 0
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* 1 1 channel 3 - Socket 1
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* Note: Above is abstracted from Schemetic. But actually it seems to be other way.
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* 1 0 channel 2 - Socket 1
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* 1 1 channel 3 - Socket 0
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* Note: The DIMMs need to be plugged in from the farthest slot for each channel.
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*/
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//backup = sp5100_set_gpio(SP5100_GPIO49_52, 0x1, 0x1);
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//sp5100_set_gpio(SP5100_GPIO37_46_47_48, (~i2c_channel & 1) << 3, 0x1 << 3);
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spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
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if (spdAddress == 0)
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return AGESA_ERROR;
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/*
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* SMBus Base Address was set during southbridge early setup.
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* e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000, CIMX using 0xB00 as default
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*/
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sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0);
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ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0);
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setupFch(ioBase);
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status = readspd(ioBase, spdAddress, (void *)info->Buffer, 256);
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for (i=0; i<256; i++) {
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printk(BIOS_DEBUG, "%02X ", info->Buffer[i]);
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if ((i%16)==15)
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printk(BIOS_DEBUG, "\n");
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}
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printk(BIOS_DEBUG, "\n");
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//sp5100_restore_gpio(SP5100_GPIO49_52, backup);
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return status;
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}
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