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sb/intel/common: Rename TCO timeout 

Rename TCO1_TIMEOUT to TCO_TIMEOUT to match rest of the tree.

Change-Id: Ib136e9b2d0006eb4ceceb298b557644760d1185c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Kyösti Mälkki 2022-11-25 12:12:34 +02:00
parent 307320c23f
commit 28c6df7323
3 changed files with 3 additions and 3 deletions
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2
src/southbridge/intel/bd82x6x/pch.h
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@ -466,7 +466,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap);
#if CONFIG(TCO_SPACE_NOT_YET_SPLIT) #if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
#define TCO1_STS 0x64 #define TCO1_STS 0x64
#define TCO1_TIMEOUT (1 << 3) #define TCO_TIMEOUT (1 << 3)
#define DMISCI_STS (1 << 9) #define DMISCI_STS (1 << 9)
#define TCO2_STS 0x66 #define TCO2_STS 0x66
#define TCO2_STS_SECOND_TO (1 << 1) #define TCO2_STS_SECOND_TO (1 << 1)

2
src/southbridge/intel/common/tco.h
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@ -13,7 +13,7 @@
#define PMBASE_TCO_OFFSET 0x60 #define PMBASE_TCO_OFFSET 0x60
#define TCO1_STS 0x04 #define TCO1_STS 0x04
#define TCO1_TIMEOUT (1 << 3) #define TCO_TIMEOUT (1 << 3)
#define TCO2_STS 0x06 #define TCO2_STS 0x06
#define TCO2_STS_SECOND_TO (1 << 1) #define TCO2_STS_SECOND_TO (1 << 1)
#define TCO1_CNT 0x08 #define TCO1_CNT 0x08

2
src/southbridge/intel/common/watchdog.c
View File

@ -32,7 +32,7 @@ void watchdog_off(void)
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value); write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
/* Clear TCO timeout status. */ /* Clear TCO timeout status. */
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT); write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT);
write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO); write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n"); printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");