From 28d012fc4cdf9a497bbfa090f5abdca28e623b29 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 6 May 2022 17:43:44 +0200 Subject: [PATCH] vc/amd/fsp/sabrina/UsbUpd: update USB settings structure to match FSP This file started as a copy from Cezanne. Sabrina has less USB ports than Cezanne. Also the struct definition of fch_usb2_phy has changed and FSP_USB_STRUCT_MINOR_VERSION is also updated. TEST=None Signed-off-by: Felix Held Change-Id: I1ef2b62373b178d729b3230d0d8539986cc631ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/64129 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Raul Rangel --- src/vendorcode/amd/fsp/sabrina/FspUsb.h | 35 ++++++++++++++----------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/src/vendorcode/amd/fsp/sabrina/FspUsb.h b/src/vendorcode/amd/fsp/sabrina/FspUsb.h index fea1fee3bd..19fac353bb 100644 --- a/src/vendorcode/amd/fsp/sabrina/FspUsb.h +++ b/src/vendorcode/amd/fsp/sabrina/FspUsb.h @@ -4,29 +4,32 @@ #include #define FSP_USB_STRUCT_MAJOR_VERSION 0xd -#define FSP_USB_STRUCT_MINOR_VERSION 0x6 +#define FSP_USB_STRUCT_MINOR_VERSION 0xe -#define USB2_PORT_COUNT 8 -#define USB3_PORT_COUNT 4 +#define USB2_PORT_COUNT 6 +#define USB3_PORT_COUNT 3 #define USBC_COMBO_PHY_COUNT 2 struct fch_usb2_phy { - uint8_t compdstune; ///< COMPDSTUNE - uint8_t sqrxtune; ///< SQRXTUNE - uint8_t txfslstune; ///< TXFSLSTUNE - uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE - uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE - uint8_t txrisetune; ///< TXRISETUNE - uint8_t txvreftune; ///< TXVREFTUNE - uint8_t txhsxvtune; ///< TXHSXVTUNE - uint8_t txrestune; ///< TXRESTUNE + uint8_t compdistune; ///< COMPDISTUNE + uint8_t pllbtune; ///< PLLBTUNE + uint8_t pllitune; ///< PLLITUNE + uint8_t pllptune; ///< PLLPTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE } __packed; struct fch_usb3_phy { - uint8_t tx_term_ctrl; ///< tx_term_ctrl - uint8_t rx_term_ctrl; ///< rx_term_ctrl - uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN - uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL + uint8_t tx_term_ctrl; ///< tx_term_ctrl + uint8_t rx_term_ctrl; ///< rx_term_ctrl + uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN + uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL } __packed; #define USB0_PORT0 0