soc/intel: Use config_of_path(SA_DEVFN_ROOT)

We do not want to disguise somewhat complex function
calls as simple macros.

Change-Id: I53324603c9ece1334c6e09d51338084166f7a585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/fizz/mainboard.c

@@ -221,8 +221,7 @@ static unsigned long mainboard_write_acpi_tables(
 
 static void mainboard_enable(struct device *dev)
 {
-	struct device *root = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf = root->chip_info;
 
 	mainboard_set_power_limits(conf);
 

src/mainboard/google/poppy/variants/atlas/mainboard.c

@@ -37,8 +37,7 @@ static uint32_t get_pl2(void)
 /* Override dev tree settings per board */
 void variant_devtree_update(void)
 {
-	struct device *root = SA_DEV_ROOT;
+	config_t *cfg = config_of_path(SA_DEVFN_ROOT);
-	config_t *cfg = root->chip_info;
 
 	/* Update PL2 based on CPU */
 	cfg->tdp_pl2_override = get_pl2();

src/mainboard/google/poppy/variants/nami/mainboard.c

@@ -234,11 +234,11 @@ void variant_devtree_update(void)
 	uint32_t sku_id = variant_board_sku();
 	uint32_t i;
 	int oem_index;
-	struct device *root = SA_DEV_ROOT;
-	config_t *cfg = root->chip_info;
 	uint8_t pl2_id = PL2_ID_DEFAULT;
 	struct device *spi_fpmcu = PCH_DEV_GSPI1;
 
+	config_t *cfg = config_of_path(SA_DEVFN_ROOT);
+
 	switch (sku_id) {
 	case SKU_0_SONA:
 	case SKU_1_SONA:

src/mainboard/google/poppy/variants/nautilus/mainboard.c

@@ -41,11 +41,11 @@ const char *smbios_system_sku(void)
 void variant_devtree_update(void)
 {
 	uint32_t sku_id = variant_board_sku();
-	struct device *root = SA_DEV_ROOT;
-	config_t *cfg = root->chip_info;
 	uint16_t abase;
 	uint32_t val32;
 
+	config_t *cfg = config_of_path(SA_DEVFN_ROOT);
+
 	switch (sku_id) {
 	case SKU_0_NAUTILUS:
 		/* Disable LTE module */

src/mainboard/google/poppy/variants/nocturne/mainboard.c

@@ -38,8 +38,7 @@ static uint32_t get_pl2(void)
 /* Override dev tree settings per board */
 void variant_devtree_update(void)
 {
-	struct device *root = SA_DEV_ROOT;
+	config_t *cfg = config_of_path(SA_DEVFN_ROOT);
-	config_t *cfg = root->chip_info;
 
 	/* Update PL2 based on CPU */
 	cfg->tdp_pl2_override = get_pl2();

src/soc/intel/apollolake/acpi.c

@@ -90,7 +90,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 void acpi_create_gnvs(struct global_nvs_t *gnvs)
 {
 	struct soc_intel_apollolake_config *cfg;
-	struct device *dev = SA_DEV_ROOT;
+	cfg = config_of_path(SA_DEVFN_ROOT);
 
 	/* Clear out GNVS. */
 	memset(gnvs, 0, sizeof(*gnvs));
@@ -110,12 +110,6 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs)
 	/* CPU core count */
 	gnvs->pcnt = dev_count_cpu();
 
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-	cfg = dev->chip_info;
-
 	/* Enable DPTF based on mainboard configuration */
 	gnvs->dpte = cfg->dptf_enable;
 
@@ -158,7 +152,7 @@ int soc_madt_sci_irq_polarity(int sci)
 void soc_fill_fadt(acpi_fadt_t *fadt)
 {
 	const struct soc_intel_apollolake_config *cfg;
-	struct device *dev = SA_DEV_ROOT;
+	cfg = config_of_path(SA_DEVFN_ROOT);
 
 	fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
 
@@ -174,13 +168,8 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 	fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR;
 
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-	cfg = dev->chip_info;
 
-	if(cfg->lpss_s0ix_enable)
+	if (cfg->lpss_s0ix_enable)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 

src/soc/intel/apollolake/chip.c

@@ -295,24 +295,18 @@ static void pcie_override_devicetree_after_silicon_init(void)
 static void set_power_limits(void)
 {
 	static struct soc_intel_apollolake_config *cfg;
-	struct device *dev = SA_DEV_ROOT;
 	msr_t rapl_msr_reg, limit;
 	uint32_t power_unit;
 	uint32_t tdp, min_power, max_power;
 	uint32_t pl2_val;
 
+	cfg = config_of_path(SA_DEVFN_ROOT);
+
 	if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
 		printk(BIOS_INFO, "Skip the RAPL settings.\n");
 		return;
 	}
 
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-
-	cfg = dev->chip_info;
-
 	/* Get units */
 	rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT);
 	power_unit = 1 << (rapl_msr_reg.lo & 0xf);
@@ -368,15 +362,9 @@ static void set_power_limits(void)
 static void set_sci_irq(void)
 {
 	static struct soc_intel_apollolake_config *cfg;
-	struct device *dev = SA_DEV_ROOT;
 	uint32_t scis;
 
-	if (!dev || !dev->chip_info) {
+	cfg = config_of_path(SA_DEVFN_ROOT);
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-
-	cfg = dev->chip_info;
 
 	/* Change only if a device tree entry exists. */
 	if (cfg->sci_irq) {
@@ -550,7 +538,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
 
 static void parse_devicetree(FSP_S_CONFIG *silconfig)
 {
-	struct device *dev = SA_DEV_ROOT;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 
 	if (!dev) {
 		printk(BIOS_ERR, "Could not find root device\n");
@@ -679,21 +667,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 {
 	FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
 	static struct soc_intel_apollolake_config *cfg;
+	struct device *dev;
 
 	/* Load VBT before devicetree-specific config. */
 	silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get();
 
-	struct device *dev = SA_DEV_ROOT;
+	dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-
+	cfg = config_of(dev);
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
 
 	mainboard_devtree_update(dev);
 
-	cfg = dev->chip_info;
-
 	/* Parse device tree and disable unused device*/
 	parse_devicetree(silconfig);
 

src/soc/intel/apollolake/cpu.c

@@ -295,14 +295,7 @@ void cpu_lock_sgx_memory(void)
 
 int soc_fill_sgx_param(struct sgx_param *sgx_param)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	assert(dev != NULL);
-	config_t *conf = dev->chip_info;
-
-	if (!conf) {
-		printk(BIOS_ERR, "Failed to get chip_info for SGX param\n");
-		return -1;
-	}
 
 	sgx_param->enable = conf->sgx_enable;
 	return 0;

src/soc/intel/apollolake/pmutil.c

@@ -148,13 +148,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 {
 	DEVTREE_CONST struct soc_intel_apollolake_config *config;
 
-	/* Look up the device in devicetree */
+	config = config_of_path(SA_DEVFN_ROOT);
-	DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-	config = dev->chip_info;
 
 	/* Assign to out variable */
 	*dw0 = config->gpe0_dw1;

src/soc/intel/apollolake/pnpconfig.c

@@ -37,8 +37,10 @@ static void pnp_settings(void *unused)
 	int index;
 	size_t arrsize;
 	const struct pnpconfig *pnpconfigarr;
-	struct device *dev = SA_DEV_ROOT;
+	struct soc_intel_apollolake_config *config;
-	struct soc_intel_apollolake_config *config = dev->chip_info;
+
+	config = config_of_path(SA_DEVFN_ROOT);
+
 	switch (config->pnp_settings) {
 	case PNP_PERF:
 		pnpconfigarr = perf;

src/soc/intel/apollolake/romstage.c

@@ -100,17 +100,8 @@ static void soc_early_romstage_init(void)
 /* Thermal throttle activation offset */
 static void configure_thermal_target(void)
 {
-	const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-	if (!dev) {
-		printk(BIOS_ERR, "Could not find SOC devicetree config\n");
-		return;
-	}
-	const config_t *conf = dev->chip_info;
-	if (!dev->chip_info) {
-		printk(BIOS_ERR, "Could not find chip info\n");
-		return;
-	}
 	msr_t msr;
+	const config_t *conf = config_of_path(SA_DEVFN_ROOT);
 
 	if (!conf->tcc_offset)
 		return;

src/soc/intel/broadwell/acpi.c

@@ -386,12 +386,12 @@ static void generate_T_state_entries(int core, int cores_per_package)
 
 static void generate_C_state_entries(void)
 {
-	struct device *dev = SA_DEV_ROOT;
-	config_t *config = dev->chip_info;
 	acpi_cstate_t map[3];
 	int *set;
 	int i;
 
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
+
 	if (config->s0ix_enable)
 		set = cstate_set_s0ix;
 	else

src/soc/intel/broadwell/cpu.c

@@ -195,8 +195,7 @@ static int pcode_mailbox_write(u32 command, u32 data)
 
 static void initialize_vr_config(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
 	printk(BIOS_DEBUG, "Initializing VR config.\n");
@@ -450,10 +449,10 @@ static void configure_c_states(void)
 
 static void configure_thermal_target(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
+
 	/* Set TCC activation offset if supported */
 	msr = rdmsr(MSR_PLATFORM_INFO);
 	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {

src/soc/intel/broadwell/smmrelocate.c

@@ -270,7 +270,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	struct device *dev = SA_DEV_ROOT;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 
 	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
 

src/soc/intel/cannonlake/acpi.c

@@ -144,8 +144,9 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 				ARRAY_SIZE(cstate_set_non_s0ix))];
 	int *set;
 	int i;
-	struct device *dev = SA_DEV_ROOT;
+
-	config_t *config = dev->chip_info;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
+
 	int is_s0ix_enable = config->s0ix_enable;
 
 	if (is_s0ix_enable) {
@@ -165,18 +166,18 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 
 void soc_power_states_generation(int core_id, int cores_per_package)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
-	config_t *config = dev->chip_info;
+
-	if (config->eist_enable)
 	/* Generate P-state tables */
+	if (config->eist_enable)
 		generate_p_state_entries(core_id, cores_per_package);
 }
 
 void soc_fill_fadt(acpi_fadt_t *fadt)
 {
 	const uint16_t pmbase = ACPI_BASE_ADDRESS;
-	const struct device *dev = PCH_DEV_LPC;
+	const struct soc_intel_cannonlake_config *config;
-	const struct soc_intel_cannonlake_config *config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_LPC);
 
 	if (!config->PmTimerDisabled) {
 		fadt->pm_tmr_blk = pmbase + PM1_TMR;
@@ -200,8 +201,8 @@ uint32_t soc_read_sci_irq_select(void)
 
 void acpi_create_gnvs(struct global_nvs_t *gnvs)
 {
-	const struct device *dev = PCH_DEV_LPC;
+	const struct soc_intel_cannonlake_config *config;
-	const struct soc_intel_cannonlake_config *config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_LPC);
 
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;

src/soc/intel/cannonlake/chip.c

@@ -170,12 +170,7 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
 static void soc_fill_gpio_pm_configuration(void)
 {
 	uint8_t value[TOTAL_GPIO_COMM];
-	const struct device *dev;
+	const config_t *config = config_of_path(SA_DEVFN_ROOT);
-	dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0);
-	if (!dev || !dev->chip_info)
-		return;
-
-	const config_t *config = dev->chip_info;
 
 	if (config->gpio_override_pm)
 		memcpy(value, config->gpio_pm, sizeof(uint8_t) *

src/soc/intel/cannonlake/cpu.c

@@ -105,8 +105,8 @@ void set_power_limits(u8 power_limit_1_time)
 	unsigned int power_unit;
 	unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
 	u8 power_limit_1_val;
-	struct device *dev = SA_DEV_ROOT;
+
-	config_t *conf = dev->chip_info;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
 
 	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
 		power_limit_1_time = 28;
@@ -234,11 +234,10 @@ static void soc_fsp_load(void)
 
 static void configure_isst(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
-	if (conf && conf->speed_shift_enable) {
+	if (conf->speed_shift_enable) {
 		/*
 		 * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
 		 * is supported or not. coreboot needs to configure MSR 0x1AA
@@ -260,12 +259,7 @@ static void configure_isst(void)
 
 static void configure_misc(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	if (!dev) {
-		printk(BIOS_ERR, "SA_DEV_ROOT device not found!\n");
-		return;
-	}
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
@@ -367,8 +361,7 @@ static void configure_c_states(void)
 
 static void configure_thermal_target(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
 	/* Set TCC activation offset if supported */

src/soc/intel/cannonlake/fsp_params.c

@@ -97,13 +97,7 @@ static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params)
 
 static void parse_devicetree(FSP_S_CONFIG *params)
 {
-	struct device *dev = SA_DEV_ROOT;
+	const config_t *config = config_of_path(SA_DEVFN_ROOT);
-	if (!dev) {
-		printk(BIOS_ERR, "Could not find root device\n");
-		return;
-	}
-
-	const config_t *config = dev->chip_info;
 
 	parse_devicetree_param(config, params);
 }
@@ -147,8 +141,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	int i;
 	FSP_S_CONFIG *params = &supd->FspsConfig;
 	FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
-	struct device *dev = SA_DEV_ROOT;
+	struct device *dev;
-	config_t *config = dev->chip_info;
+
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
 
 	/* Parse device tree and enable/disable devices */
 	parse_devicetree(params);

src/soc/intel/cannonlake/pmc.c

@@ -153,8 +153,7 @@ static void pch_power_options(void)
 
 static void pmc_init(void *unused)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
-	config_t *config = dev->chip_info;
 
 	rtc_init();
 

src/soc/intel/cannonlake/smmrelocate.c

@@ -256,7 +256,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	struct device *dev = SA_DEV_ROOT;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 
 	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
 

src/soc/intel/common/block/chip/chip.c

@@ -21,13 +21,8 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void)
 {
 	const struct soc_intel_common_config *soc_config;
 	const config_t *config;
-	int devfn = SA_DEVFN_ROOT;
-	const struct device *dev = pcidev_path_on_root(devfn);
 
-	if (!dev || !dev->chip_info)
+	config = config_of_path(SA_DEVFN_ROOT);
-		die("Could not find SA_DEV_ROOT devicetree config!\n");
-
-	config = dev->chip_info;
 	soc_config = &config->common_soc_config;
 
 	return soc_config;

src/soc/intel/denverton_ns/memmap.c

@@ -30,7 +30,7 @@ static inline uintptr_t system_agent_region_base(size_t reg)
 #if defined(__SIMPLE_DEVICE__)
 	pci_devfn_t dev = SA_DEV_ROOT;
 #else
-	struct device *dev = SA_DEV_ROOT;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 #endif
 	/* All regions concerned for have 1 MiB alignment. */
 	return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);

src/soc/intel/icelake/acpi.c

@@ -137,8 +137,9 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 				ARRAY_SIZE(cstate_set_non_s0ix))];
 	int *set;
 	int i;
-	struct device *dev = SA_DEV_ROOT;
+
-	config_t *config = dev->chip_info;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
+
 	int is_s0ix_enable = config->s0ix_enable;
 
 	if (is_s0ix_enable) {
@@ -158,8 +159,8 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
 
 void soc_power_states_generation(int core_id, int cores_per_package)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
-	config_t *config = dev->chip_info;
+
 	if (config->eist_enable)
 		/* Generate P-state tables */
 		generate_p_state_entries(core_id, cores_per_package);
@@ -168,8 +169,8 @@ void soc_power_states_generation(int core_id, int cores_per_package)
 void soc_fill_fadt(acpi_fadt_t *fadt)
 {
 	const uint16_t pmbase = ACPI_BASE_ADDRESS;
-	const struct device *dev = pcidev_on_root(0, 0);
+
-	const struct soc_intel_icelake_config *config = dev->chip_info;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
 
 	if (!config->PmTimerDisabled) {
 		fadt->pm_tmr_blk = pmbase + PM1_TMR;
@@ -193,8 +194,7 @@ uint32_t soc_read_sci_irq_select(void)
 
 void acpi_create_gnvs(struct global_nvs_t *gnvs)
 {
-	const struct device *dev = pcidev_on_root(0, 0);
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
-	const struct soc_intel_icelake_config *config = dev->chip_info;
 
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;

src/soc/intel/icelake/chip.c

@@ -107,12 +107,7 @@ const char *soc_acpi_name(const struct device *dev)
 static void soc_fill_gpio_pm_configuration(void)
 {
 	uint8_t value[TOTAL_GPIO_COMM];
-	const struct device *dev;
+	const config_t *config = config_of_path(SA_DEVFN_ROOT);
-	dev = pcidev_on_root(SA_DEV_SLOT_ROOT, 0);
-	if (!dev || !dev->chip_info)
-		return;
-
-	const config_t *config = dev->chip_info;
 
 	if (config->gpio_override_pm)
 		memcpy(value, config->gpio_pm, sizeof(uint8_t) *

src/soc/intel/icelake/cpu.c

@@ -40,8 +40,7 @@ static void soc_fsp_load(void)
 
 static void configure_isst(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
 	if (conf->speed_shift_enable) {
@@ -66,10 +65,10 @@ static void configure_isst(void)
 
 static void configure_misc(void)
 {
-	struct device *dev = SA_DEV_ROOT;
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
+
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */

src/soc/intel/icelake/fsp_params.c

@@ -29,13 +29,8 @@
 
 static void parse_devicetree(FSP_S_CONFIG *params)
 {
-	struct device *dev = pcidev_on_root(0, 0);
+	const struct soc_intel_icelake_config *config;
-	if (!dev) {
+	config = config_of_path(SA_DEVFN_ROOT);
-		printk(BIOS_ERR, "Could not find root device\n");
-		return;
-	}
-
-	const struct soc_intel_icelake_config *config = dev->chip_info;
 
 	for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
 		params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
@@ -55,8 +50,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
 	int i;
 	FSP_S_CONFIG *params = &supd->FspsConfig;
-	struct device *dev = SA_DEV_ROOT;
+
-	config_t *config = dev->chip_info;
+	struct device *dev;
+	struct soc_intel_icelake_config *config;
+	config = config_of_path(SA_DEVFN_ROOT);
 
 	/* Parse device tree and enable/disable devices */
 	parse_devicetree(params);

src/soc/intel/icelake/pmc.c

@@ -135,8 +135,7 @@ static void pch_power_options(void)
 
 static void pmc_init(void *unused)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
-	config_t *config = dev->chip_info;
 
 	rtc_init();
 

src/soc/intel/icelake/smmrelocate.c

@@ -255,7 +255,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	struct device *dev = SA_DEV_ROOT;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 
 	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
 

src/soc/intel/skylake/acpi.c

@@ -174,8 +174,7 @@ static int get_cores_per_package(void)
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
-	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC);
-	const struct soc_intel_skylake_config *config = dev->chip_info;
 
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
@@ -234,9 +233,8 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 void acpi_fill_fadt(acpi_fadt_t *fadt)
 {
-	const struct device *dev = SA_DEV_ROOT;
-	const config_t *config = dev ? dev->chip_info : NULL;
 	const uint16_t pmbase = ACPI_BASE_ADDRESS;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
 
 	/* Use ACPI 3.0 revision */
 	fadt->header.revision = get_acpi_table_revision(FADT);
@@ -284,7 +282,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
 			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
 
-	if (config && config->s0ix_enable)
+	if (config->s0ix_enable)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 
 	fadt->reset_reg.space_id = 1;
@@ -506,8 +504,7 @@ void generate_cpu_entries(struct device *device)
 	int totalcores = dev_count_cpu();
 	int cores_per_package = get_cores_per_package();
 	int numcpus = totalcores/cores_per_package;
-	struct device *dev = SA_DEV_ROOT;
+	config_t *config = config_of_path(SA_DEVFN_ROOT);
-	config_t *config = dev->chip_info;
 	int is_s0ix_enable = config->s0ix_enable;
 	int max_c_state;
 
@@ -519,7 +516,7 @@ void generate_cpu_entries(struct device *device)
 	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
 	       numcpus, cores_per_package);
 
-	if (config && config->eist_enable && config->speed_shift_enable) {
+	if (config->eist_enable && config->speed_shift_enable) {
 		struct cppc_config cppc_config;
 		cpu_init_cppc_config(&cppc_config, 2 /* version 2 */);
 		acpigen_write_CPPC_package(&cppc_config);
@@ -619,11 +616,11 @@ unsigned long northbridge_write_acpi_tables(struct device *const dev,
 					    unsigned long current,
 					    struct acpi_rsdp *const rsdp)
 {
-	const struct soc_intel_skylake_config *const config = dev->chip_info;
+	const struct soc_intel_skylake_config *const config = config_of(dev);
 	acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
 
 	/* Create DMAR table only if we have VT-d capability. */
-	if ((config && config->ignore_vtd) || !soc_is_vtd_capable())
+	if (config->ignore_vtd || !soc_is_vtd_capable())
 		return current;
 
 	printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
@@ -695,8 +692,7 @@ void southbridge_inject_dsdt(struct device *device)
 /* Save wake source information for calculating ACPI _SWS values */
 int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
 {
-	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC);
-	const struct soc_intel_skylake_config *config = dev->chip_info;
 	struct chipset_power_state *ps;
 	static uint32_t gpe0_sts[GPE0_REG_MAX];
 	uint32_t pm1_en;

src/soc/intel/skylake/chip_fsp20.c

@@ -233,15 +233,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	FSP_S_CONFIG *params = &supd->FspsConfig;
 	FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig;
 	static struct soc_intel_skylake_config *config;
+	struct device *dev;
 	uintptr_t vbt_data = (uintptr_t)vbt_get();
 	int i;
 
-	struct device *dev = SA_DEV_ROOT;
+	config = config_of_path(SA_DEVFN_ROOT);
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-	config = dev->chip_info;
 
 	mainboard_silicon_init_params(params);
 	/* Set PsysPmax if it is available from DT */

src/soc/intel/skylake/cpu.c

@@ -116,8 +116,8 @@ void set_power_limits(u8 power_limit_1_time)
 	unsigned int power_unit;
 	unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1;
 	u8 power_limit_1_val;
-	struct device *dev = SA_DEV_ROOT;
+
-	config_t *conf = dev->chip_info;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
 
 	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
 		power_limit_1_time = 28;
@@ -240,13 +240,13 @@ void set_power_limits(u8 power_limit_1_time)
 
 static void configure_thermal_target(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
+
 	/* Set TCC activation offset if supported */
 	msr = rdmsr(MSR_PLATFORM_INFO);
-	if ((msr.lo & (1 << 30)) && conf && conf->tcc_offset) {
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
 		msr = rdmsr(MSR_TEMPERATURE_TARGET);
 		msr.lo &= ~(0xf << 24); /* Bits 27:24 */
 		msr.lo |= (conf->tcc_offset & 0xf) << 24;
@@ -260,10 +260,10 @@ static void configure_thermal_target(void)
 
 static void configure_isst(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
+
 	if (conf->speed_shift_enable) {
 		/*
 		* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
@@ -286,21 +286,19 @@ static void configure_isst(void)
 
 static void configure_misc(void)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	if (!dev) {
-		printk(BIOS_ERR, "SA_DEV_ROOT device not found!\n");
-		return;
-	}
-	config_t *conf = dev->chip_info;
 	msr_t msr;
 
+
 	msr = rdmsr(IA32_MISC_ENABLE);
 	msr.lo |= (1 << 0);	/* Fast String enable */
 	msr.lo |= (1 << 3);	/* TM1/TM2/EMTTM enable */
+
 	if (conf->eist_enable)
 		msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
 	else
 		msr.lo &= ~(1 << 16);	/* Enhanced SpeedStep Disable */
+
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	/* Disable Thermal interrupts */
@@ -558,19 +556,7 @@ void cpu_lock_sgx_memory(void)
 
 int soc_fill_sgx_param(struct sgx_param *sgx_param)
 {
-	struct device *dev = SA_DEV_ROOT;
+	config_t *conf = config_of_path(SA_DEVFN_ROOT);
-	config_t *conf;
-
-	if (!dev) {
-		printk(BIOS_ERR, "Failed to get root dev for checking SGX param\n");
-		return -1;
-	}
-
-	conf = dev->chip_info;
-	if (!conf) {
-		printk(BIOS_ERR, "Failed to get chip_info for SGX param\n");
-		return -1;
-	}
 
 	sgx_param->enable = conf->sgx_enable;
 	return 0;

src/soc/intel/skylake/pmc.c

@@ -181,7 +181,7 @@ static void config_deep_sx(uint32_t deepsx_config)
 
 void pmc_soc_init(struct device *dev)
 {
-	const config_t *config = dev->chip_info;
+	const config_t *config = config_of(dev);
 
 	rtc_init();
 
@@ -233,12 +233,7 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL);
  */
 static void pm1_handle_wake_pin(void *unused)
 {
-	struct device *dev = SA_DEV_ROOT;
+	const config_t *conf = config_of_path(SA_DEVFN_ROOT);
-
-	if (!dev || !dev->chip_info)
-		return;
-
-	const config_t *conf = dev->chip_info;
 
 	/* If WAKE# pin is enabled, bail out early. */
 	if (conf->deep_sx_config & DSX_EN_WAKE_PIN)

src/soc/intel/skylake/romstage/systemagent.c

@@ -26,13 +26,11 @@
 
 static void systemagent_vtd_init(void)
 {
-	const struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	const struct soc_intel_skylake_config *config = NULL;
 
-	if (root_dev)
+	config = config_of_path(SA_DEVFN_ROOT);
-		config = root_dev->chip_info;
+	if (config->ignore_vtd)
-	if (config && config->ignore_vtd)
 		return;
 
 	const bool vtd_capable =

src/soc/intel/skylake/smmrelocate.c

@@ -265,7 +265,7 @@ static void setup_ied_area(struct smm_relocation_params *params)
 void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
 				size_t *smm_save_state_size)
 {
-	struct device *dev = SA_DEV_ROOT;
+	struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 
 	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");