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soc/mediatek: Move SPMI interface configuration to SoC folder 

The SPMI interface configuration is SoC-dependent.
- MT8192 and MT8195 are the same.
- MT8186 does not need to implement this.
- MT8188 is different from MT8195, and we will submit another patch to
  fix this.

BUG=b:249436110
TEST=build pass.
BRANCH=corsola

Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sen Chu 2022-10-18 13:41:09 +08:00 committed by Felix Held
parent 1543252e5f
commit 28dceaec71
5 changed files with 73 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/mediatek/common/include/soc/pmif_spmi.h
View File

@ -10,6 +10,9 @@
#define DEFAULT_VALUE_READ_TEST (0x5a)
#define DEFAULT_VALUE_WRITE_TEST (0xa5)
#define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG)
#define PMIF_CMD_PER_1_3 ((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG))
struct mtk_rgu_regs {
u32 reserved[36];
u32 wdt_swsysrst2;
@ -85,4 +88,5 @@ extern const size_t spmi_dev_cnt;
int pmif_spmi_init(struct pmif *arb);
int spmi_config_master(void);
void pmif_spmi_iocfg(void);
void pmif_spmi_config(struct pmif *arb, int mstid);
#endif /* __SOC_MEDIATEK_PMIF_SPMI_H__ */

25
src/soc/mediatek/common/pmif_spmi.c
View File

@ -8,9 +8,6 @@
#include <soc/pmif_sw.h>
#include <soc/spmi.h>
#define PMIF_CMD_PER_3 (0x1 << PMIF_CMD_EXT_REG_LONG)
#define PMIF_CMD_PER_1_3 ((0x1 << PMIF_CMD_REG) | (0x1 << PMIF_CMD_EXT_REG_LONG))
/* SPMI_MST, SPMI_SAMPL_CTRL */
DEFINE_BIT(SAMPL_CK_POL, 0)
DEFINE_BITFIELD(SAMPL_CK_DLY, 3, 1)
@ -25,6 +22,11 @@ DEFINE_BIT(SPI_EINT_MODE_GATING_EN, 13)
DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0)
DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9)
__weak void pmif_spmi_config(struct pmif *arb, int mstid)
{
/* Do nothing. */
}
static int spmi_read_check(struct pmif *pmif_arb, int slvid)
{
u32 rdata = 0;
@ -127,23 +129,8 @@ static void pmif_spmi_enable_cmdIssue(int mstid, bool en)
static void pmif_spmi_enable(int mstid)
{
struct pmif *arb = get_pmif_controller(PMIF_SPMI, mstid);
u32 cmd_per;
/* clear all cmd permission for per channel */
write32(&arb->mtk_pmif->inf_cmd_per_0, 0);
write32(&arb->mtk_pmif->inf_cmd_per_1, 0);
write32(&arb->mtk_pmif->inf_cmd_per_2, 0);
write32(&arb->mtk_pmif->inf_cmd_per_3, 0);
/* enable if we need cmd 0~3 permission for per channel */
cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 |
PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 |
PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 |
PMIF_CMD_PER_1_3 << 0;
write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per);
cmd_per = PMIF_CMD_PER_3 << 4;
write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per);
pmif_spmi_config(arb, mstid);
/*
* set bytecnt max limitation.

21
src/soc/mediatek/mt8188/pmif_spmi.c
View File

@ -61,6 +61,27 @@ int spmi_config_master(void)
return 0;
}
void pmif_spmi_config(struct pmif *arb, int mstid)
{
u32 cmd_per;
/* Clear all cmd permission for per channel */
write32(&arb->mtk_pmif->inf_cmd_per_0, 0);
write32(&arb->mtk_pmif->inf_cmd_per_1, 0);
write32(&arb->mtk_pmif->inf_cmd_per_2, 0);
write32(&arb->mtk_pmif->inf_cmd_per_3, 0);
/* TODO: figure out correct setting for MT8188 */
cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 |
PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 |
PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 |
PMIF_CMD_PER_1_3 << 0;
write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per);
cmd_per = PMIF_CMD_PER_3 << 4;
write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per);
}
void pmif_spmi_iocfg(void)
{
SET32_BITFIELDS(&mtk_iocfg_lt->eh_cfg_clr, SPMI_SCL, 0x7, SPMI_SDA, 0x7);

21
src/soc/mediatek/mt8192/pmif_spmi.c
View File

@ -56,6 +56,27 @@ int spmi_config_master(void)
return 0;
}
void pmif_spmi_config(struct pmif *arb, int mstid)
{
u32 cmd_per;
/* Clear all cmd permission for per channel */
write32(&arb->mtk_pmif->inf_cmd_per_0, 0);
write32(&arb->mtk_pmif->inf_cmd_per_1, 0);
write32(&arb->mtk_pmif->inf_cmd_per_2, 0);
write32(&arb->mtk_pmif->inf_cmd_per_3, 0);
/* Enable if we need cmd 0~3 permission for per channel */
cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 |
PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 |
PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 |
PMIF_CMD_PER_1_3 << 0;
write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per);
cmd_per = PMIF_CMD_PER_3 << 4;
write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per);
}
void pmif_spmi_iocfg(void)
{
SET32_BITFIELDS(&mtk_iocfg_bm->drv_cfg2, SPMI_SCL, 0x2, SPMI_SDA, 0x2);

21
src/soc/mediatek/mt8195/pmif_spmi.c
View File

@ -66,6 +66,27 @@ int spmi_config_master(void)
return 0;
}
void pmif_spmi_config(struct pmif *arb, int mstid)
{
u32 cmd_per;
/* Clear all cmd permission for per channel */
write32(&arb->mtk_pmif->inf_cmd_per_0, 0);
write32(&arb->mtk_pmif->inf_cmd_per_1, 0);
write32(&arb->mtk_pmif->inf_cmd_per_2, 0);
write32(&arb->mtk_pmif->inf_cmd_per_3, 0);
/* Enable if we need cmd 0~3 permission for per channel */
cmd_per = PMIF_CMD_PER_3 << 28 | PMIF_CMD_PER_3 << 24 |
PMIF_CMD_PER_3 << 20 | PMIF_CMD_PER_3 << 16 |
PMIF_CMD_PER_3 << 8 | PMIF_CMD_PER_3 << 4 |
PMIF_CMD_PER_1_3 << 0;
write32(&arb->mtk_pmif->inf_cmd_per_0, cmd_per);
cmd_per = PMIF_CMD_PER_3 << 4;
write32(&arb->mtk_pmif->inf_cmd_per_1, cmd_per);
}
void pmif_spmi_iocfg(void)
{
SET32_BITFIELDS(&mtk_iocfg_bm->eh_cfg_clr, SPMI_SCL, 0x7, SPMI_SDA, 0x7);