diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index d6e8f53ee4..7859b53318 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -63,19 +63,19 @@ void fast_spi_init(void)
 /*
  * Set FAST_SPIBAR BIOS Control register based on input bit field.
  */
-static void fast_spi_set_bios_control_reg(uint8_t bios_cntl_bit)
+static void fast_spi_set_bios_control_reg(uint32_t bios_cntl_bit)
 {
 #if defined(__SIMPLE_DEVICE__)
 	pci_devfn_t dev = PCH_DEV_SPI;
 #else
 	struct device *dev = PCH_DEV_SPI;
 #endif
-	uint8_t bc_cntl;
+	uint32_t bc_cntl;
 
 	assert((bios_cntl_bit & (bios_cntl_bit - 1)) == 0);
-	bc_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL);
+	bc_cntl = pci_read_config32(dev, SPIBAR_BIOS_CONTROL);
 	bc_cntl |= bios_cntl_bit;
-	pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bc_cntl);
+	pci_write_config32(dev, SPIBAR_BIOS_CONTROL, bc_cntl);
 }
 
 /*
@@ -106,6 +106,19 @@ void fast_spi_set_lock_enable(void)
 	fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
 }
 
+/*
+ * Set FAST_SPIBAR BIOS Control EXT BIOS LE bit.
+ */
+void fast_spi_set_ext_bios_lock_enable(void)
+{
+	if (!CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
+		return;
+
+	fast_spi_set_bios_control_reg(SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE);
+
+	fast_spi_read_post_write(SPIBAR_BIOS_CONTROL);
+}
+
 /*
  * Set FAST_SPIBAR BIOS Control EISS bit.
  */
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
index 883c3ce3eb..ce4eb2d7c2 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h
@@ -14,6 +14,7 @@
 /* Bit definitions for BIOS_CONTROL */
 #define SPIBAR_BIOS_CONTROL_WPD		(1 << 0)
 #define SPIBAR_BIOS_CONTROL_LOCK_ENABLE	(1 << 1)
+#define SPIBAR_BIOS_CONTROL_EXT_BIOS_LOCK_ENABLE	(1 << 28)
 #define SPIBAR_BIOS_CONTROL_CACHE_DISABLE	(1 << 2)
 #define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE	(1 << 3)
 #define SPIBAR_BIOS_CONTROL_EISS	(1 << 5)
diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
index e3ffa6a39a..e742a27a42 100644
--- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h
+++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h
@@ -22,6 +22,10 @@ void fast_spi_set_bios_interface_lock_down(void);
  * Set FAST_SPIBAR BIOS Control LE bit.
  */
 void fast_spi_set_lock_enable(void);
+/*
+ * Set FAST_SPIBAR BIOS Control Ext Bios LE bit.
+ */
+void fast_spi_set_ext_bios_lock_enable(void);
 /*
  * Set FAST_SPIBAR BIOS Control EISS bit.
  */
diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c
index 906f8b02c6..b10306edcb 100644
--- a/src/soc/intel/common/pch/lockdown/lockdown.c
+++ b/src/soc/intel/common/pch/lockdown/lockdown.c
@@ -63,6 +63,9 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown)
 
 		/* BIOS Lock */
 		fast_spi_set_lock_enable();
+
+		/* EXT BIOS Lock */
+		fast_spi_set_ext_bios_lock_enable();
 	}
 }