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Add suport for normal register dumping on ite8510E/TE/G 

Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Anders Juel Jensen 2010-08-22 19:41:47 +00:00 committed by Stefan Reinauer
parent 3d0ff918f8
commit 28e4af5801
1 changed files with 60 additions and 0 deletions
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60
util/superiotool/ite.c
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@ -95,6 +95,66 @@ static const struct superio_registers reg_table[] = {
{0x00,0x00,0x6a,0x00,0x6e,0x01,0x01,EOT}},
{EOT}}},
{0x8510, "IT8510E/TE/G", {
{NOLDN, "Chip ID",
{0x20,0x21, EOT},
{0x85,0x10, EOT}},
{NOLDN, "Chip Version",
{0x22,EOT},
{0x21,EOT}},
{NOLDN, "Super I/O Control Reigster (SIOCTRL)",
{0x23,EOT},
{0x01,EOT}},
{NOLDN, "Super I/O Configuration Register (SIOIRQ)",
{0x25,EOT},
{0x00,EOT}},
{NOLDN, "Super I/O General Purpose Register (SIOGP)",
{0x26,EOT},
{0x00,EOT}},
{NOLDN, "Super I/O Power Mode Register (SIOPWR)",
{0x2d,EOT},
{0x00,EOT}},
{NOLDN, "Logical Device Activate Register (LDA)",
{0x30,EOT},
{0x00,EOT}},
{NOLDN, "I/O Port Base Address for Descriptor 0 (IOBAD0)",
{0x60,0x61,EOT},
{NANA,NANA,EOT}},
{NOLDN, "I/O Port Base Address for Descriptor 1 (IOBAD1)",
{0x62,0x63,EOT},
{NANA,NANA,EOT}},
{NOLDN, "Interupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)",
{0x70,EOT},
{NANA,EOT}},
{NOLDN, "Interrupt Request Type Select (IRQTP)",
{0x71,EOT},
{NANA,EOT}},
{NOLDN, "DMA Channel Select 0 (DMAS0)",
{0x74,EOT},
{0x04,EOT}},
{NOLDN, "DMA Channel Select 1 (DMAS1)",
{0x75,EOT},
{0x04,EOT}},
{0x4, "System Wakup-Up (SWUC)",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
{0x00,0x00,0x00,0x00,0x00,0x00,0x03,EOT}},
{0x5, "Keyboard/Mouse",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
{0x00,0x00,0x00,0x00,0x00,0x0c,0x03,EOT}},
{0x6, "Keyboard/Mouse",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
{0x00,0x00,0x60,0x00,0x64,0x01,0x03,EOT}},
{0xf, "Shared Memory/Flash Interface (SMFI)",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,0xf5,0xf6,0xf7,0xf8,EOT},
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}},
{0x10, "Real Time Clock (RTC)",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,0xf1,0xf2,EOT},
{0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x00,0x49,0x4a,EOT}},
{0x11, "Power Management Interface Channel 1",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
{0x00,0x00,0x62,0x00,0x66,0x01,0x03,EOT}},
{0x12, "Power Management Interface Channel 2",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT},
{0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}},
{EOT}}},
{0x8511, "IT8511E/TE/G", {
{NOLDN, NULL,