diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 11a0daa9cc..8508d8fcdd 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -28,6 +28,7 @@ config CHROMEOS
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select INTEL_LPSS_UART_FOR_CONSOLE
+	select DRIVERS_INTEL_USB4_RETIMER
 	select DRIVERS_WWAN_FM350GL
 
 config MAINBOARD_DIR
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
index 07985a30bd..850f0e5f05 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
@@ -121,8 +121,30 @@ chip soc/intel/meteorlake
 				end
 			end
 		end
-		device ref tcss_dma0 on end
-		device ref tcss_dma1 on end
+		device ref tcss_dma0 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port1 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port2 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
+				use tcss_usb3_port4 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
 		device ref pcie_rp7  on
 			# Enable PCH PCIE RP 7 using CLK 1
 			register "pcie_rp[PCIE_RP(7)]" = "{