GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/intel/mtlrvp: Describe mainboard configuration for BB Retimer 

This patch describes BB retimer for tcss_dma0 and tcss_dma1 with respect
to GPP_B21 as per schematics.

+--------------+------------+
| tbt_pcie_rp0 |  tcss_dma0 |
+--------------+------------+
| tbt_pcie_rp1 |  tcss_dma0 |
+--------------+------------+
| tbt_pcie_rp2 |  tcss_dma1 |
+--------------+------------+
| tbt_pcie_rp3 |  tcss_dma1 |
+--------------+------------+

BUG=b:224325352
BRANCH=None
TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration
of tbt_pcie_rp as part of lspci.
00:07.0 PCI bridge: Intel Corporation Device 7ec4
00:07.1 PCI bridge: Intel Corporation Device 7ec5
00:07.2 PCI bridge: Intel Corporation Device 7ec6
00:07.3 PCI bridge: Intel Corporation Device 7ec7

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ie1a0026b064aa4f7fcd27e75c0b0d052ec620dcc
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72786
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Harsha B R 2023-02-04 16:09:05 +05:30 committed by Sridhar Siricilla
parent 5897382269
commit 2904aeabad
2 changed files with 25 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/intel/mtlrvp/Kconfig
View File

@ -28,6 +28,7 @@ config CHROMEOS
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select INTEL_LPSS_UART_FOR_CONSOLE select INTEL_LPSS_UART_FOR_CONSOLE
select DRIVERS_INTEL_USB4_RETIMER
select DRIVERS_WWAN_FM350GL select DRIVERS_WWAN_FM350GL
config MAINBOARD_DIR config MAINBOARD_DIR

26
src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb
View File

@ -121,8 +121,30 @@ chip soc/intel/meteorlake
end end
end end
end end
device ref tcss_dma0 on end device ref tcss_dma0 on
device ref tcss_dma1 on end chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
chip drivers/intel/usb4/retimer
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port2 as dfp[1].typec_port
device generic 0 on end
end
end
device ref tcss_dma1 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port3 as dfp[0].typec_port
device generic 0 on end
end
chip drivers/intel/usb4/retimer
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
use tcss_usb3_port4 as dfp[1].typec_port
device generic 0 on end
end
end
device ref pcie_rp7 on device ref pcie_rp7 on
# Enable PCH PCIE RP 7 using CLK 1 # Enable PCH PCIE RP 7 using CLK 1
register "pcie_rp[PCIE_RP(7)]" = "{ register "pcie_rp[PCIE_RP(7)]" = "{