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mb/pcengines/apu2: add and use IOMUX defines 

Add GPIO IOMUX defines for the pins that are used in the mainboard code
which enables using the PAD_GPI and PAD_GPO macros.

TEST=Timeless build for APU2/3/4/5 results in identical binary.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie32df9ed2cb6a5670a29cff91e085a3585c8bcf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Felix Held 2021-08-05 19:43:48 +02:00
parent 4b027690b6
commit 2909b487a2
2 changed files with 30 additions and 24 deletions
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14
src/mainboard/pcengines/apu2/gpio_ftns.h
View File

@ -26,4 +26,18 @@ int get_spd_offset(void);
#define GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5)
#define GPIO_71 0x4D // PROCHOT
#define GPIO_22_IOMUX_GPIOxx 0
#define GPIO_32_IOMUX_GPIOxx 0
#define GPIO_33_IOMUX_GPIOxx 0
#define GPIO_49_IOMUX_GPIOxx 2
#define GPIO_50_IOMUX_GPIOxx 2
#define GPIO_51_IOMUX_GPIOxx 2
#define GPIO_55_IOMUX_GPIOxx 3
#define GPIO_57_IOMUX_GPIOxx 1
#define GPIO_58_IOMUX_GPIOxx 1
#define GPIO_59_IOMUX_GPIOxx 3
#define GPIO_64_IOMUX_GPIOxx 2
#define GPIO_68_IOMUX_GPIOxx 0
#define GPIO_71_IOMUX_GPIOxx 0
#endif /* GPIO_FTNS_H */

40
src/mainboard/pcengines/apu2/romstage.c
View File

@ -31,39 +31,31 @@ void board_BeforeAgesa(struct sysinfo *cb)
}
const struct soc_amd_gpio gpio_common[] = {
/* Output disabled, pull up/down disabled */
PAD_CFG_STRUCT(GPIO_49, Function2, PAD_PULL(PULL_NONE)),
PAD_CFG_STRUCT(GPIO_50, Function2, PAD_PULL(PULL_NONE)),
PAD_CFG_STRUCT(GPIO_71, Function0, PAD_PULL(PULL_NONE)),
/* Output enabled, value low, pull up/down disabled */
PAD_CFG_STRUCT(GPIO_57, Function1, PAD_OUTPUT(LOW)),
PAD_CFG_STRUCT(GPIO_58, Function1, PAD_OUTPUT(LOW)),
PAD_CFG_STRUCT(GPIO_59, Function3, PAD_OUTPUT(LOW)),
/* Output enabled, value high, pull up/down disabled */
PAD_CFG_STRUCT(GPIO_51, Function2, PAD_OUTPUT(HIGH)),
PAD_CFG_STRUCT(GPIO_55, Function3, PAD_OUTPUT(HIGH)),
PAD_CFG_STRUCT(GPIO_64, Function2, PAD_OUTPUT(HIGH)),
PAD_CFG_STRUCT(GPIO_68, Function0, PAD_OUTPUT(HIGH)),
PAD_GPI(GPIO_49, PULL_NONE),
PAD_GPI(GPIO_50, PULL_NONE),
PAD_GPI(GPIO_71, PULL_NONE),
PAD_GPO(GPIO_57, LOW),
PAD_GPO(GPIO_58, LOW),
PAD_GPO(GPIO_59, LOW),
PAD_GPO(GPIO_51, HIGH),
PAD_GPO(GPIO_55, HIGH),
PAD_GPO(GPIO_64, HIGH),
PAD_GPO(GPIO_68, HIGH),
};
const struct soc_amd_gpio gpio_apu2[] = {
/* Output disabled, pull up/down disabled */
PAD_CFG_STRUCT(GPIO_32, Function0, PAD_PULL(PULL_NONE)),
PAD_GPI(GPIO_32, PULL_NONE),
};
const struct soc_amd_gpio gpio_apu34[] = {
/* Output disabled, pull up/down disabled */
PAD_CFG_STRUCT(GPIO_32, Function0, PAD_PULL(PULL_NONE)),
/* Output enabled, value low, pull up/down disabled */
PAD_CFG_STRUCT(GPIO_33, Function0, PAD_OUTPUT(LOW)),
PAD_GPI(GPIO_32, PULL_NONE),
PAD_GPO(GPIO_33, LOW),
};
const struct soc_amd_gpio gpio_apu5[] = {
/* Output disabled, pull up/down disabled */
PAD_CFG_STRUCT(GPIO_22, Function0, PAD_PULL(PULL_NONE)),
/* Output enabled, value high, pull up/down disabled */
PAD_CFG_STRUCT(GPIO_32, Function0, PAD_OUTPUT(HIGH)),
PAD_CFG_STRUCT(GPIO_33, Function0, PAD_OUTPUT(HIGH)),
PAD_GPI(GPIO_22, PULL_NONE),
PAD_GPO(GPIO_32, HIGH),
PAD_GPO(GPIO_33, HIGH),
};
static void early_lpc_init(void)