From 290a59284e97498f6cc879ec5638af87d4538b80 Mon Sep 17 00:00:00 2001
From: Marc Jones <marcj303@gmail.com>
Date: Thu, 9 Nov 2017 12:25:02 -0700
Subject: [PATCH] soc/amd/stoneyridge: Add CPU PPKG ASL

Add PPKG Method for processor passive thermal control list.

BUG=b:67999819

Change-Id: I5d84832af06f64c923485926e4e0c73c65a2b0b2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22399
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
---
 src/soc/amd/stoneyridge/acpi/cpu.asl | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl
index 9da1550269..5d29a55089 100644
--- a/src/soc/amd/stoneyridge/acpi/cpu.asl
+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl
@@ -30,3 +30,20 @@ External (\_PR.CP04, DeviceObj)
 External (\_PR.CP05, DeviceObj)
 External (\_PR.CP06, DeviceObj)
 External (\_PR.CP07, DeviceObj)
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Return (Package ()
+		{
+			\_PR.CP00,
+			\_PR.CP01
+		})
+	} Else {
+		Return (Package ()
+		{
+			\_PR.CP00
+		})
+	}
+}