From 2911823289d6469970f46514193705c863c42113 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 1 Feb 2024 20:25:02 +0100 Subject: [PATCH] soc/amd/phoenix/fch: only call gpp_clk_setup in FSP case The configuration of the PCIe clock generators in the FCH was moved from the FSP to coreboot, since all registers are documented. This initialization is however tightly integrated in the rest of the PCIe init code inside the reference code. In the FSP case, this code was manually removed. openSIL will do that part of the initialization so that there's no coreboot-specific change needed in openSIL. This will also avoid the problems caused by mismatching configurations done by the coreboot code and the PCIe init part of the reference code. Signed-off-by: Felix Held Change-Id: I6d64285a301ade6860c07e62dcb1a718e7a96644 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80295 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/soc/amd/phoenix/fch.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index c2f0558f1a..e9bc80a505 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -200,7 +200,9 @@ void fch_init(void *chip_info) acpi_pm_gpe_add_events_print_events(); gpio_add_events(); - gpp_clk_setup(); + if (CONFIG(PLATFORM_USES_FSP2_0)) + gpp_clk_setup(); + fch_clk_output_48Mhz(); cgpll_clock_gate_init(); }