soc/intel/denverton_ns: Enable common block PMC

Mainly update headers to build.

Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.

Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

src/soc/intel/apollolake/Kconfig

@@ -61,6 +61,7 @@ config CPU_SPECIFIC_OPTIONS
 	select POSTCAR_CONSOLE
 	select POSTCAR_STAGE
 	select PMC_INVALID_READ_AFTER_WRITE
+	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select REG_SCRIPT
 	select RTC
 	select SMM_TSEG

src/soc/intel/cannonlake/Kconfig

@@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SMM_TSEG
 	select SMP
 	select SOC_AHCI_PORT_IMPLEMENTED_INVERT
+	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK

src/soc/intel/common/block/pmc/Kconfig

@@ -37,3 +37,11 @@ config PMC_INVALID_READ_AFTER_WRITE
 	help
 	  Enable this for PMC devices where a read back of ACPI BAR and
 	  IO access bit does not return the previously written value.
+
+config PMC_GLOBAL_RESET_ENABLE_LOCK
+	bool
+	help
+	  Enable this for PMC devices where the reset configuration
+	  and lock register is located under PMC BASE at offset ETR.
+	  Note that the reset register is still at 0xCF9 this only
+	  controls the enable and lock feature.

src/soc/intel/common/block/pmc/pmclib.c

@@ -419,6 +419,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps)
 	return ps->prev_sleep_state;
 }
 
+#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK)
 /*
  * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
  * This lock is reset on cold boot, hard reset, soft reset and Sx.
@@ -451,6 +452,7 @@ void pmc_global_reset_enable(bool enable)
 	reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
 	write32((void *)etr, reg);
 }
+#endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK
 
 int vboot_platform_is_resuming(void)
 {

src/soc/intel/denverton_ns/Kconfig

@@ -46,6 +46,8 @@ config CPU_SPECIFIC_OPTIONS
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOC_INTEL_COMMON_BLOCK
 	select SOC_INTEL_COMMON_BLOCK_CPU
+	select SOC_INTEL_COMMON_BLOCK_PMC
+	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 #	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_GPIO

src/soc/intel/denverton_ns/acpi.c

@@ -130,7 +130,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt)
 	fadt->pm1b_cnt_blk = 0x0;
 	fadt->pm2_cnt_blk = pmbase + PM2_CNT;
 	fadt->pm_tmr_blk = pmbase + PM1_TMR;
-	fadt->gpe0_blk = pmbase + GPE0_STS;
+	fadt->gpe0_blk = pmbase + GPE0_STS(GPE_STD);
 	fadt->gpe1_blk = 0;
 
 	/* Control Registers - Length */

src/soc/intel/denverton_ns/include/soc/iomap.h

@@ -29,6 +29,7 @@
 /* Southbridge internal device IO BARs (Set to match FSP settings) */
 #define DEFAULT_PMBASE 0x1800
 #define DEFAULT_ACPI_BASE DEFAULT_PMBASE
+#define ACPI_BASE_ADDRESS DEFAULT_PMBASE
 #define DEFAULT_TCO_BASE 0x400
 
 /* Southbridge internal device MEM BARs (Set to match FSP settings) */

src/soc/intel/denverton_ns/include/soc/pm.h

@@ -20,10 +20,9 @@
 
 #include <arch/io.h>
 #include <soc/pmc.h>
+#include <arch/acpi.h>
 
-#define SLEEP_STATE_S0 0
-#define SLEEP_STATE_S3 3
-#define SLEEP_STATE_S5 5
+#define GPE_MAX 127
 
 struct chipset_power_state {
 	uint16_t pm1_sts;
@@ -31,8 +30,8 @@ struct chipset_power_state {
 	uint32_t pm1_cnt;
 	uint16_t tco1_sts;
 	uint16_t tco2_sts;
-	uint32_t gpe0_sts[4];
-	uint32_t gpe0_en[4];
+	uint32_t gpe0_sts[GPE0_REG_MAX];
+	uint32_t gpe0_en[GPE0_REG_MAX];
 	uint32_t gen_pmcon_a;
 	uint32_t gen_pmcon_b;
 	uint32_t gblrst_cause[2];

src/soc/intel/denverton_ns/include/soc/pmc.h

@@ -120,7 +120,10 @@
 #define GPE_CTRL 0x40
 #define SWGPE_CTRL	(1 << 17)
 #define PM2_CNT 0x50
-#define GPE0_STS 0x80
+#define GPE0_REG_MAX		4
+#define GPE0_REG_SIZE		32
+#define GPE0_STS(x) (0x80 + (x * 4))
+#define  GPE_STD 0
 #define GPIO31_STS (1 << 31)
 #define GPIO30_STS (1 << 30)
 #define GPIO29_STS (1 << 29)
@@ -166,7 +169,7 @@
 #define IE_SCI_STS (1 << 3)
 #define SWGPE_STS (1 << 2)
 #define HOT_PLUG_STS (1 << 1)
-#define GPE0_EN 0x90
+#define GPE0_EN(x) (0x90 + (x * 4))
 #define GPIO31_EN (1 << 31)
 #define GPIO30_EN (1 << 30)
 #define GPIO29_EN (1 << 29)
@@ -236,6 +239,12 @@
 #define TCO2_CNT 0x0a
 #define TCO_TMR 0x12
 
+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
+#define PRSTS			0x10
+#define GPIO_GPE_CFG		0x120
+#define  GPE0_DWX_MASK		0x7
+#define GPE0_DW_SHIFT(x)	(4 + 4*(x))
+
 /* I/O ports */
 #define RST_CNT 0xcf9
 #define FULL_RST (1 << 3)

src/soc/intel/denverton_ns/pmutil.c

@@ -189,17 +189,17 @@ uint32_t clear_tco_status(void) { return print_tco_status(reset_tco_status()); }
 void enable_gpe(uint32_t mask)
 {
 	uint16_t pmbase = get_pmbase();
-	uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN));
+	uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
 	gpe0_en |= mask;
-	outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN));
+	outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
 }
 
 void disable_gpe(uint32_t mask)
 {
 	uint16_t pmbase = get_pmbase();
-	uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN));
+	uint32_t gpe0_en = inl((uint16_t)(pmbase + GPE0_EN(GPE_STD)));
 	gpe0_en &= ~mask;
-	outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN));
+	outl(gpe0_en, (uint16_t)(pmbase + GPE0_EN(GPE_STD)));
 }
 
 void disable_all_gpe(void) { disable_gpe(~0); }
@@ -207,8 +207,8 @@ void disable_all_gpe(void) { disable_gpe(~0); }
 static uint32_t reset_gpe_status(void)
 {
 	uint16_t pmbase = get_pmbase();
-	uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS));
-	outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS));
+	uint32_t gpe_sts = inl((uint16_t)(pmbase + GPE0_STS(GPE_STD)));
+	outl(gpe_sts, (uint16_t)(pmbase + GPE0_STS(GPE_STD)));
 	return gpe_sts;
 }
 

src/soc/intel/skylake/Kconfig

@@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SA_ENABLE_DPR
 	select SMM_TSEG
 	select SMP
+	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK