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soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC 

The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Sean Rhodes 2022-07-28 20:50:49 +01:00 committed by Martin Roth
parent e72ff319fd
commit 291758ddba
1 changed files with 6 additions and 2 deletions
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8
src/soc/intel/apollolake/acpi/northbridge.asl
View File

@ -11,8 +11,12 @@ Device (MCHC)
OperationRegion (MCHP, PCI_Config, 0x00, 0x100)
Field (MCHP, DWordAcc, NoLock, Preserve)
{
Offset(0x60),
MCNF, 32, /* PCI MMCONF base */
Offset (0x60), /* PCIEXBAR (0:0:0:60)
PXEN, 1, /* Enable */
PXSZ, 2, /* PCI Express Size */
, 25,
PXBR, 11, /* PCI Express Base Address */
Offset (0xA8),
TUUD, 64, /* Top of Upper Used Memory */
Offset(0xB4),