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superio/nuvoton: Add chip support for setting IRQs to edge/level 

Change-Id: I08b9eef9d6b0f120c17c3293f1f90b847742dc06
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/6064
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
This commit is contained in:
Dave Frodin 2014-06-12 16:28:21 -06:00
parent da2daef4b4
commit 29179f0735
3 changed files with 99 additions and 1 deletions
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28
src/superio/nuvoton/nct5104d/chip.h Normal file
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@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_NUVOTON_NCT5104D_CHIP_H
#define SUPERIO_NUVOTON_NCT5104D_CHIP_H
struct superio_nuvoton_nct5104d_config {
u8 irq_trigger_type;
};
#endif

6
src/superio/nuvoton/nct5104d/nct5104d.h
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@ -22,6 +22,12 @@
#ifndef SUPERIO_NUVOTON_NCT5104D_H
#define SUPERIO_NUVOTON_NCT5104D_H
/* SIO global configuration */
#define IRQ_TYPE_SEL_CR10 0x10 /* UARTA,UARTB */
#define IRQ_TYPE_SEL_CR11 0x11 /* SMI,UARTC,UARTD,WDTO */
#define GLOBAL_OPTION_CR26 0x26
#define CR26_LOCK_REG (1 << 4) /* required to access CR10/CR11 */
/* Logical Device Numbers (LDN). */
#define NCT5104D_FDC 0x00 /* FDC - not pinned out */
#define NCT5104D_SP1 0x02 /* UARTA */

66
src/superio/nuvoton/nct5104d/superio.c
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@ -23,9 +23,69 @@
#include <superio/conf_mode.h>
#include <stdlib.h>
#include "nct5104d.h"
#include "chip.h"
static void nct5104d_init(device_t dev)
{
struct superio_nuvoton_nct5104d_config *conf = dev->chip_info;
u8 reg10, reg11, reg26;
if (!dev->enabled)
return;
pnp_enter_conf_mode(dev);
//Before accessing CR10 OR CR11 Bit 4 in CR26 must be set to 1
reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
reg26 |= CR26_LOCK_REG;
pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
switch(dev->path.pnp.device) {
//SP1 (UARTA) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 5
case NCT5104D_SP1:
reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
if (conf->irq_trigger_type)
reg10 |= (1 << 5);
else
reg10 &= ~(1 << 5);
pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
break;
//SP2 (UARTB) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 4
case NCT5104D_SP2:
reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
if (conf->irq_trigger_type)
reg10 |= (1 << 4);
else
reg10 &= ~(1 << 4);
pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
break;
//SP3 (UARTC) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 5
case NCT5104D_SP3:
reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
if (conf->irq_trigger_type)
reg11 |= (1 << 5);
else
reg11 &= ~(1 << 5);
pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
break;
//SP4 (UARTD) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 4
case NCT5104D_SP4:
reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
if (conf->irq_trigger_type)
reg11 |= (1 << 4);
else
reg11 &= ~(1 << 4);
pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
break;
default:
break;
}
//Clear access control register
reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
reg26 &= ~CR26_LOCK_REG;
pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
pnp_exit_conf_mode(dev);
}
static struct device_operations ops = {
@ -38,13 +98,17 @@ static struct device_operations ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, NCT5104D_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_FDC, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
{ &ops, NCT5104D_GPIO_WDT},
{ &ops, NCT5104D_GPIO_PP_OD},
{ &ops, NCT5104D_GPIO0},
{ &ops, NCT5104D_GPIO1},
{ &ops, NCT5104D_GPIO6},
{ &ops, NCT5104D_PORT80},
};
static void enable_dev(struct device *dev)