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soc/intel/alderlake/romstage: Do initial SoC commit till romstage

Browse source 
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Add SA EDS document number and chapter number
4. Fill required FSP-M UPD to call FSP-M API

Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2020-09-09 13:34:18 +05:30
parent eb17b475c8
commit 292afef2fb
19 changed files with 1471 additions and 0 deletions
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30
src/soc/intel/alderlake/Kconfig
View file

@ -8,15 +8,22 @@ if SOC_INTEL_ALDERLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CPU_INTEL_COMMON
select FSP_M_XIP
select INTEL_DESCRIPTOR_MODE_CAPABLE
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
select MRC_SETTINGS_PROTECT
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_SA
@ -120,6 +127,13 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
config C_ENV_BOOTBLOCK_SIZE
hex
default 0xC000
@ -139,4 +153,20 @@ config FSP_FD_PATH
string
depends on FSP_USE_REPO
default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
int "Debug Consent for ADL"
# USB DBC is more common for developers so make this default to 3 if
# SOC_INTEL_DEBUG_CONSENT=y
default 3 if SOC_INTEL_DEBUG_CONSENT
default 0
help
This is to control debug interface on SOC.
Setting non-zero value will allow to use DBC or DCI to debug SOC.
PlatformDebugConsent in FspmUpd.h has the details.
Desired platform debug type are
0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
6:Enable (2-wire DCI OOB), 7:Manual
endif

14
src/soc/intel/alderlake/Makefile.inc
View file

@ -1,8 +1,22 @@
ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE),y)
subdirs-y += romstage
subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/x86/lapic
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/smm
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/cpu.c
bootblock-y += bootblock/pch.c
bootblock-y += bootblock/report_platform.c
bootblock-y += espi.c
bootblock-y += p2sb.c
romstage-y += espi.c
romstage-y += meminit.c
romstage-y += reset.c
CPPFLAGS_common += -I$(src)/soc/intel/alderlake
CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include
endif

348
src/soc/intel/alderlake/chip.h Normal file
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@ -0,0 +1,348 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_CHIP_H_
#define _SOC_CHIP_H_
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/cfg.h>
#include <intelblocks/gpio.h>
#include <intelblocks/gspi.h>
#include <soc/gpe.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <stdint.h>
#define MAX_HD_AUDIO_DMIC_LINKS 2
#define MAX_HD_AUDIO_SNDW_LINKS 4
#define MAX_HD_AUDIO_SSP_LINKS 6
struct soc_intel_alderlake_config {
/* Common struct containing soc config data required by common code */
struct soc_intel_common_config common_soc_config;
/* Gpio group routed to each dword of the GPE0 block. Values are
* of the form PMC_GPP_[A:U] or GPD. */
uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */
uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */
uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */
/* Generic IO decode ranges */
uint32_t gen1_dec;
uint32_t gen2_dec;
uint32_t gen3_dec;
uint32_t gen4_dec;
/* Enable S0iX support */
int s0ix_enable;
/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
uint8_t TcssD3HotDisable;
/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
uint8_t TcssD3ColdDisable;
/* Enable DPTF support */
int dptf_enable;
/* Deep SX enable for both AC and DC */
int deep_s3_enable_ac;
int deep_s3_enable_dc;
int deep_s5_enable_ac;
int deep_s5_enable_dc;
/* Deep Sx Configuration
* DSX_EN_WAKE_PIN - Enable WAKE# pin
* DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
* DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */
uint32_t deep_sx_config;
/* TCC activation offset */
uint32_t tcc_offset;
/* System Agent dynamic frequency support. Only effects ULX/ULT CPUs.
* When enabled memory will be training at two different frequencies.
* 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2,
* 4:FixedPoint3, 5:Enabled */
enum {
SaGv_Disabled,
SaGv_FixedPoint0,
SaGv_FixedPoint1,
SaGv_FixedPoint2,
SaGv_FixedPoint3,
SaGv_Enabled,
} SaGv;
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;
/* USB related */
struct usb2_port_config usb2_ports[16];
struct usb3_port_config usb3_ports[10];
/* Wake Enable Bitmap for USB2 ports */
uint16_t usb2_wake_enable_bitmap;
/* Wake Enable Bitmap for USB3 ports */
uint16_t usb3_wake_enable_bitmap;
/* SATA related */
uint8_t SataEnable;
uint8_t SataMode;
uint8_t SataSalpSupport;
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
/*
* Enable(0)/Disable(1) SATA Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the SATA Power Optimizer.
*/
uint8_t SataPwrOptimizeDisable;
/*
* SATA Port Enable Dito Config.
* Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
*/
uint8_t SataPortsEnableDitoConfig[8];
/* SataPortsDmVal is the DITO multiplier. Default is 15. */
uint8_t SataPortsDmVal[8];
/* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */
uint16_t SataPortsDitoVal[8];
/* Audio related */
uint8_t PchHdaDspEnable;
uint8_t PchHdaAudioLinkHdaEnable;
uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
uint8_t PchHdaIDispLinkTmode;
uint8_t PchHdaIDispLinkFrequency;
uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */
uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];
/* PCIe RP L1 substate */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,
L1_SS_DISABLED,
L1_SS_L1_1,
L1_SS_L1_2,
} PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR: Enable (1) / Disable (0) */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
/* Integrated Sensor */
uint8_t PchIshEnable;
/* Heci related */
uint8_t Heci3Enabled;
/* Gfx related */
enum {
IGD_SM_0MB = 0x00,
IGD_SM_32MB = 0x01,
IGD_SM_64MB = 0x02,
IGD_SM_96MB = 0x03,
IGD_SM_128MB = 0x04,
IGD_SM_160MB = 0x05,
IGD_SM_4MB = 0xF0,
IGD_SM_8MB = 0xF1,
IGD_SM_12MB = 0xF2,
IGD_SM_16MB = 0xF3,
IGD_SM_20MB = 0xF4,
IGD_SM_24MB = 0xF5,
IGD_SM_28MB = 0xF6,
IGD_SM_36MB = 0xF8,
IGD_SM_40MB = 0xF9,
IGD_SM_44MB = 0xFA,
IGD_SM_48MB = 0xFB,
IGD_SM_52MB = 0xFC,
IGD_SM_56MB = 0xFD,
IGD_SM_60MB = 0xFE,
} IgdDvmt50PreAlloc;
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;
uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
/* PL2 Override value in Watts */
uint32_t tdp_pl2_override;
/* Intel Speed Shift Technology */
uint8_t speed_shift_enable;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;
/* Enable C6 DRAM */
uint8_t enable_c6dram;
/*
* PRMRR size setting with below options
* Disable: 0x0
* 32MB: 0x2000000
* 64MB: 0x4000000
* 128 MB: 0x8000000
* 256 MB: 0x10000000
* 512 MB: 0x20000000
*/
uint32_t PrmrrSize;
uint8_t PmTimerDisabled;
/*
* SerialIO device mode selection:
* PchSerialIoDisabled,
* PchSerialIoPci,
* PchSerialIoHidden,
* PchSerialIoLegacyUart,
* PchSerialIoSkipInit
*/
uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
/*
* GSPIn Default Chip Select Mode:
* 0:Hardware Mode,
* 1:Software Mode
*/
uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/*
* GSPIn Default Chip Select State:
* 0: Low,
* 1: High
*/
uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
/* Debug interface selection */
enum {
DEBUG_INTERFACE_RAM = (1 << 0),
DEBUG_INTERFACE_UART_8250IO = (1 << 1),
DEBUG_INTERFACE_USB3 = (1 << 3),
DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4),
DEBUG_INTERFACE_TRACEHUB = (1 << 5),
} debug_interface_flag;
/* Enable Pch iSCLK */
uint8_t pch_isclk;
/* CNVi */
uint8_t CnviMode;
uint8_t CnviBtCore;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
enum {
FORCE_DISABLE,
FORCE_ENABLE,
} CnviBtAudioOffload;
/*
* SOC Aux orientation override:
* This is a bitfield that corresponds to up to 4 TCSS ports on ADL.
* Even numbered bits (0, 2, 4, 6) control the retimer being handled by SOC.
* Odd numbered bits (1, 3, 5, 7) control the orientation of the physical aux lines
* on the motherboard.
*/
uint16_t TcssAuxOri;
/* Connect Topology Command timeout value */
uint16_t ITbtConnectTopologyTimeoutInMs;
/*
* Override GPIO PM configuration:
* 0: Use FSP default GPIO PM program,
* 1: coreboot to override GPIO PM program
*/
uint8_t gpio_override_pm;
/*
* GPIO PM configuration: 0 to disable, 1 to enable power gating
* Bit 6-7: Reserved
* Bit 5: MISCCFG_GPSIDEDPCGEN
* Bit 4: MISCCFG_GPRCOMPCDLCGEN
* Bit 3: MISCCFG_GPRTCDLCGEN
* Bit 2: MISCCFG_GSXLCGEN
* Bit 1: MISCCFG_GPDPCGEN
* Bit 0: MISCCFG_GPDLCGEN
*/
uint8_t gpio_pm[TOTAL_GPIO_COMM];
/* DP config */
/*
* Port config
* 0:Disabled, 1:eDP, 2:MIPI DSI
*/
uint8_t DdiPortAConfig;
uint8_t DdiPortBConfig;
/* Enable(1)/Disable(0) HPD */
uint8_t DdiPortAHpd;
uint8_t DdiPortBHpd;
uint8_t DdiPortCHpd;
uint8_t DdiPort1Hpd;
uint8_t DdiPort2Hpd;
uint8_t DdiPort3Hpd;
uint8_t DdiPort4Hpd;
/* Enable(1)/Disable(0) DDC */
uint8_t DdiPortADdc;
uint8_t DdiPortBDdc;
uint8_t DdiPortCDdc;
uint8_t DdiPort1Ddc;
uint8_t DdiPort2Ddc;
uint8_t DdiPort3Ddc;
uint8_t DdiPort4Ddc;
/* Hybrid storage mode enable (1) / disable (0)
* This mode makes FSP detect Optane and NVME and set PCIe lane mode
* accordingly */
uint8_t HybridStorageMode;
/*
* Override CPU flex ratio value:
* CPU ratio value controls the maximum processor non-turbo ratio.
* Valid Range 0 to 63.
*
* In general descriptor provides option to set default cpu flex ratio.
* Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
* That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
*
* Only override CPU flex ratio if don't want to boot with non-turbo max.
*/
uint8_t cpu_ratio_override;
/*
* Enable(0)/Disable(1) DMI Power Optimizer on PCH side.
* Default 0. Setting this to 1 disables the DMI Power Optimizer.
*/
uint8_t DmiPwrOptimizeDisable;
/*
* Enable(1)/Disable(0) CPU Replacement check.
* Default 0. Setting this to 1 to check CPU replacement.
*/
uint8_t CpuReplacementCheck;
/* ISA Serial Base selection. */
enum {
ISA_SERIAL_BASE_ADDR_3F8,
ISA_SERIAL_BASE_ADDR_2F8,
} IsaSerialUartBase;
};
typedef struct soc_intel_alderlake_config config_t;
#endif

51
src/soc/intel/alderlake/espi.c Normal file
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@ -0,0 +1,51 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is created based on Intel Alder Lake Processor PCH Datasheet
* Document number: 621483
* Chapter number: 2
*/
#include <device/pci.h>
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <soc/espi.h>
#include <soc/iomap.h>
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
/*
* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
* certain memory range as reserved range for BIOS usage.
* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
*/
static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = {
{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
{ 0, 0 }
};
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
{
return lpc_fixed_mmio_ranges;
}
void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
{
const config_t *config = config_of(dev);
gen_io_dec[0] = config->gen1_dec;
gen_io_dec[1] = config->gen2_dec;
gen_io_dec[2] = config->gen3_dec;
gen_io_dec[3] = config->gen4_dec;
}
void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec)
{
/* Mirror these same settings in DMI PCR */
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);
pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);
}

121
src/soc/intel/alderlake/include/soc/gpe.h Normal file
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@ -0,0 +1,121 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_GPE_H_
#define _SOC_GPE_H_
/* GPE_31_0 */
#define GPE0_DW0_00 0
#define GPE0_DW0_01 1
#define GPE0_DW0_02 2
#define GPE0_DW0_03 3
#define GPE0_DW0_04 4
#define GPE0_DW0_05 5
#define GPE0_DW0_06 6
#define GPE0_DW0_07 7
#define GPE0_DW0_08 8
#define GPE0_DW0_09 9
#define GPE0_DW0_10 10
#define GPE0_DW0_11 11
#define GPE0_DW0_12 12
#define GPE0_DW0_13 13
#define GPE0_DW0_14 14
#define GPE0_DW0_15 15
#define GPE0_DW0_16 16
#define GPE0_DW0_17 17
#define GPE0_DW0_18 18
#define GPE0_DW0_19 19
#define GPE0_DW0_20 20
#define GPE0_DW0_21 21
#define GPE0_DW0_22 22
#define GPE0_DW0_23 23
#define GPE0_DW0_24 24
#define GPE0_DW0_25 25
#define GPE0_DW0_26 26
#define GPE0_DW0_27 27
#define GPE0_DW0_28 28
#define GPE0_DW0_29 29
#define GPE0_DW0_30 30
#define GPE0_DW0_31 31
/* GPE_63_32 */
#define GPE0_DW1_00 32
#define GPE0_DW1_01 33
#define GPE0_DW1_02 34
#define GPE0_DW1_03 36
#define GPE0_DW1_04 36
#define GPE0_DW1_05 37
#define GPE0_DW1_06 38
#define GPE0_DW1_07 39
#define GPE0_DW1_08 40
#define GPE0_DW1_09 41
#define GPE0_DW1_10 42
#define GPE0_DW1_11 43
#define GPE0_DW1_12 44
#define GPE0_DW1_13 45
#define GPE0_DW1_14 46
#define GPE0_DW1_15 47
#define GPE0_DW1_16 48
#define GPE0_DW1_17 49
#define GPE0_DW1_18 50
#define GPE0_DW1_19 51
#define GPE0_DW1_20 52
#define GPE0_DW1_21 53
#define GPE0_DW1_22 54
#define GPE0_DW1_23 55
#define GPE0_DW1_24 56
#define GPE0_DW1_25 57
#define GPE0_DW1_26 58
#define GPE0_DW1_27 59
#define GPE0_DW1_28 60
#define GPE0_DW1_29 61
#define GPE0_DW1_30 62
#define GPE0_DW1_31 63
/* GPE_95_64 */
#define GPE0_DW2_00 64
#define GPE0_DW2_01 65
#define GPE0_DW2_02 66
#define GPE0_DW2_03 67
#define GPE0_DW2_04 68
#define GPE0_DW2_05 69
#define GPE0_DW2_06 70
#define GPE0_DW2_07 71
#define GPE0_DW2_08 72
#define GPE0_DW2_09 73
#define GPE0_DW2_10 74
#define GPE0_DW2_11 75
#define GPE0_DW2_12 76
#define GPE0_DW2_13 77
#define GPE0_DW2_14 78
#define GPE0_DW2_15 79
#define GPE0_DW2_16 80
#define GPE0_DW2_17 81
#define GPE0_DW2_18 82
#define GPE0_DW2_19 83
#define GPE0_DW2_20 84
#define GPE0_DW2_21 85
#define GPE0_DW2_22 86
#define GPE0_DW2_23 87
#define GPE0_DW2_24 88
#define GPE0_DW2_25 89
#define GPE0_DW2_26 90
#define GPE0_DW2_27 91
#define GPE0_DW2_28 92
#define GPE0_DW2_29 93
#define GPE0_DW2_30 94
#define GPE0_DW2_31 95
/* GPE_STD */
#define GPE0_HOT_PLUG 97
#define GPE0_SWGPE 98
#define GPE0_TCOSCI 102
#define GPE0_SMB_WAK 103
#define GPE0_PCI_EXP 105
#define GPE0_BATLOW 106
#define GPE0_PME 107
#define GPE0_ME_SCI 108
#define GPE0_PME_B0 109
#define GPE0_ESPI 110
#define GPE0_GPIO_T2 111
#define GPE0_LAN_WAK 112
#define GPE0_WADT 114
#define GPE_MAX GPE0_WADT
#endif /* _SOC_GPE_H_ */

21
src/soc/intel/alderlake/include/soc/iomap.h
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@ -38,6 +38,27 @@
#define EDRAM_BASE_ADDRESS 0xfed80000
#define EDRAM_BASE_SIZE 0x4000
#define TBT0_BASE_ADDRESS 0xfed84000
#define TBT0_BASE_SIZE 0x1000
#define TBT1_BASE_ADDRESS 0xfed85000
#define TBT1_BASE_SIZE 0x1000
#define TBT2_BASE_ADDRESS 0xfed86000
#define TBT2_BASE_SIZE 0x1000
#define TBT3_BASE_ADDRESS 0xfed87000
#define TBT3_BASE_SIZE 0x1000
#define GFXVT_BASE_ADDRESS 0xfed90000
#define GFXVT_BASE_SIZE 0x1000
#define IPUVT_BASE_ADDRESS 0xfed92000
#define IPUVT_BASE_SIZE 0x1000
#define VTVC0_BASE_ADDRESS 0xfed91000
#define VTVC0_BASE_SIZE 0x1000
#define REG_BASE_ADDRESS 0xfb000000
#define REG_BASE_SIZE 0x1000

11
src/soc/intel/alderlake/include/soc/msr.h Normal file
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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_MSR_H_
#define _SOC_MSR_H_
#include <intelblocks/msr.h>
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_VR_MISC_CONFIG2 0x636
#endif

167
src/soc/intel/alderlake/include/soc/pmc.h Normal file
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@ -0,0 +1,167 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_ALDERLAKE_PMC_H_
#define _SOC_ALDERLAKE_PMC_H_
/* PCI Configuration Space (D31:F2): PMC */
#define PWRMBASE 0x10
#define ABASE 0x20
/* Memory mapped IO registers in PMC */
#define GEN_PMCON_A 0x1020
#define DC_PP_DIS (1 << 30)
#define DSX_PP_DIS (1 << 29)
#define AG3_PP_EN (1 << 28)
#define SX_PP_EN (1 << 27)
#define ALLOW_ICLK_PLL_SD_INC0 (1 << 26)
#define GBL_RST_STS (1 << 24)
#define DISB (1 << 23)
#define ALLOW_OPI_PLL_SD_INC0 (1 << 22)
#define MEM_SR (1 << 21)
#define ALLOW_SPXB_CG_INC0 (1 << 20)
#define ALLOW_L1LOW_C0 (1 << 19)
#define MS4V (1 << 18)
#define ALLOW_L1LOW_OPI_ON (1 << 17)
#define SUS_PWR_FLR (1 << 16)
#define PME_B0_S5_DIS (1 << 15)
#define PWR_FLR (1 << 14)
#define ALLOW_L1LOW_BCLKREQ_ON (1 << 13)
#define DIS_SLP_X_STRCH_SUS_UP (1 << 12)
#define SLP_S3_MIN_ASST_WDTH_MASK (3 << 10)
#define SLP_S3_MIN_ASST_WDTH_60USEC (0 << 10)
#define SLP_S3_MIN_ASST_WDTH_1MS (1 << 10)
#define SLP_S3_MIN_ASST_WDTH_50MS (2 << 10)
#define SLP_S3_MIN_ASST_WDTH_2S (3 << 10)
#define HOST_RST_STS (1 << 9)
#define ESPI_SMI_LOCK (1 << 8)
#define S4MAW_MASK (3 << 4)
#define S4MAW_1S (1 << 4)
#define S4MAW_2S (2 << 4)
#define S4MAW_3S (3 << 4)
#define S4MAW_4S (0 << 4)
#define S4ASE (1 << 3)
#define PER_SMI_SEL_MASK (3 << 1)
#define SMI_RATE_64S (0 << 1)
#define SMI_RATE_32S (1 << 1)
#define SMI_RATE_16S (2 << 1)
#define SMI_RATE_8S (3 << 1)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
#define GEN_PMCON_B 0x1024
#define SLP_STR_POL_LOCK (1 << 18)
#define ACPI_BASE_LOCK (1 << 17)
#define PM_DATA_BAR_DIS (1 << 16)
#define WOL_EN_OVRD (1 << 13)
#define BIOS_PCI_EXP_EN (1 << 10)
#define PWRBTN_LVL (1 << 9)
#define SMI_LOCK (1 << 4)
#define RTC_BATTERY_DEAD (1 << 2)
#define ETR 0x1048
#define CF9_LOCK (1 << 31)
#define CF9_GLB_RST (1 << 20)
#define SSML 0x104C
#define SSML_SSL_DS (0 << 0)
#define SSML_SSL_EN (1 << 0)
#define SSMC 0x1050
#define SSMC_SSMS (1 << 0)
#define SSMD 0x1054
#define SSMD_SSD_MASK (0xffff << 0)
#define PRSTS 0x1810
#define S3_PWRGATE_POL 0x1828
#define S3DC_GATE_SUS (1 << 1)
#define S3AC_GATE_SUS (1 << 0)
#define S4_PWRGATE_POL 0x182c
#define S4DC_GATE_SUS (1 << 1)
#define S4AC_GATE_SUS (1 << 0)
#define S5_PWRGATE_POL 0x1830
#define S5DC_GATE_SUS (1 << 15)
#define S5AC_GATE_SUS (1 << 14)
#define DSX_CFG 0x1834
#define REQ_CNV_NOWAKE_DSX (1 << 4)
#define REQ_BATLOW_DSX (1 << 3)
#define DSX_EN_WAKE_PIN (1 << 2)
#define DSX_DIS_AC_PRESENT_PD (1 << 1)
#define DSX_EN_LAN_WAKE_PIN (1 << 0)
#define DSX_CFG_MASK (0x1f << 0)
#define PMSYNC_TPR_CFG 0x18C4
#define PCH2CPU_TPR_CFG_LOCK (1 << 31)
#define PCH2CPU_TT_EN (1 << 26)
#define PCH_PMC_EPOC 0x18EC
#define PCH_EPOC_2LM(__epoc) ((__epoc) & 0x1)
/* XTAL frequency in bits 21, 20, 17 */
#define PCH_EPOC_XTAL_FREQ(__epoc) ((((__epoc) >> 19) & 0x6) | ((__epoc) >> 17 & 0x1))
/**
* enum pch_pmc_xtal - External crystal oscillator frequency.
* @XTAL_24_MHZ: 24 MHz external crystal.
* @XTAL_19_2_MHZ: 19.2 MHz external crystal.
* @XTAL_38_4_MHZ: 38.4 MHz external crystal.
*/
enum pch_pmc_xtal {
XTAL_24_MHZ,
XTAL_19_2_MHZ,
XTAL_38_4_MHZ,
};
/**
* pmc_get_xtal_freq() - Return frequency of external oscillator.
*
* Return &enum pch_pmc_xtal corredsponding to frequency returned by PMC.
*/
enum pch_pmc_xtal pmc_get_xtal_freq(void);
#define PCH_PWRM_ACPI_TMR_CTL 0x18FC
#define GPIO_GPE_CFG 0x1920
#define GPE0_DWX_MASK 0xf
#define GPE0_DW_SHIFT(x) (4*(x))
#define PMC_GPP_B 0x0
#define PMC_GPP_T 0x1
#define PMC_GPP_A 0x2
#define PMC_GPP_R 0x3
#define PMC_GPD 0x4
#define PMC_GPP_S 0x5
#define PMC_GPP_H 0x6
#define PMC_GPP_D 0x7
#define PMC_GPP_U 0x8
#define PMC_GPP_F 0xA
#define PMC_GPP_C 0xB
#define PMC_GPP_E 0xC
#define GBLRST_CAUSE0 0x1924
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)
#define GBLRST_CAUSE1 0x1928
#define HPR_CAUSE0 0x192C
#define HPR_CAUSE0_MI_HRPD (1 << 10)
#define HPR_CAUSE0_MI_HRPC (1 << 9)
#define HPR_CAUSE0_MI_HR (1 << 8)
#define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22)
#define IRQ_REG ACTL
#define SCI_IRQ_ADJUST 0
#define ACTL 0x1BD8
#define PWRM_EN (1 << 8)
#define ACPI_EN (1 << 7)
#define SCI_IRQ_SEL (7 << 0)
#define SCIS_IRQ9 0
#define SCIS_IRQ10 1
#define SCIS_IRQ11 2
#define SCIS_IRQ20 4
#define SCIS_IRQ21 5
#define SCIS_IRQ22 6
#define SCIS_IRQ23 7
#endif

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_ROMSTAGE_H_
#define _SOC_ROMSTAGE_H_
#include <fsp/api.h>
#include <stddef.h>
/* Provide a callback to allow mainboard to override the DRAM part number. */
const char *mainboard_get_dram_part_num(size_t *len);
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
void romstage_pch_init(void);
/* Board type */
enum board_type {
BOARD_TYPE_MOBILE = 0,
BOARD_TYPE_DESKTOP = 1,
BOARD_TYPE_ULT_ULX = 5,
BOARD_TYPE_SERVER = 7
};
#endif /* _SOC_ROMSTAGE_H_ */

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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _SOC_ALDERLAKE_SOC_CHIP_H_
#define _SOC_ALDERLAKE_SOC_CHIP_H_
#include "../../chip.h"
#endif /* _SOC_ALDERLAKE_SOC_CHIP_H_ */

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src/soc/intel/alderlake/include/soc/systemagent.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is created based on Intel Alder Lake Processor SA Datasheet
* Document number: 619503
* Chapter number: 3
*/
#ifndef SOC_ALDERLAKE_SYSTEMAGENT_H
#define SOC_ALDERLAKE_SYSTEMAGENT_H
#include <intelblocks/systemagent.h>
/* Device 0:0.0 PCI configuration space */
#define EPBAR 0x40
#define DMIBAR 0x68
#define CAPID0_A 0xe4
#define VTD_DISABLE (1 << 23)
/* MCHBAR offsets */
#define GFXVTBAR 0x5400
#define EDRAMBAR 0x5408
#define VTVC0BAR 0x5410
#define REGBAR 0x5420
#define MCH_DDR_POWER_LIMIT_LO 0x58e0
#define MCH_DDR_POWER_LIMIT_HI 0x58e4
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define MCH_PKG_POWER_LIMIT_HI 0x59a4
#define BIOS_RESET_CPL 0x5da8
#define IMRBASE 0x6a40
#define IMRLIMIT 0x6a48
#define IPUVTBAR 0x7880
#define TBT0BAR 0x7888
#define TBT1BAR 0x7890
#define TBT2BAR 0x7898
#define TBT3BAR 0x78a0
#define MAX_TBT_PCIE_PORT 4
#define VTBAR_ENABLED 0x01
#define VTBAR_MASK 0x7ffffff000ull
static const struct sa_mmio_descriptor soc_vtd_resources[] = {
{ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
{ IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" },
{ TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" },
{ TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" },
{ TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" },
{ TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" },
{ VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
};
#define V_P2SB_CFG_IBDF_BUS 0
#define V_P2SB_CFG_IBDF_DEV 30
#define V_P2SB_CFG_IBDF_FUNC 7
#define V_P2SB_CFG_HBDF_BUS 0
#define V_P2SB_CFG_HBDF_DEV 30
#define V_P2SB_CFG_HBDF_FUNC 6
#endif

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/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <assert.h>
#include <console/console.h>
#include <fsp/util.h>
#include <soc/meminit.h>
#include <spd_bin.h>
#include <string.h>
enum dimm_enable_options {
ENABLE_BOTH_DIMMS = 0,
DISABLE_DIMM0 = 1,
DISABLE_DIMM1 = 2,
DISABLE_BOTH_DIMMS = 3
};
static void spd_read_from_cbfs(const struct spd_info *spd_info,
uintptr_t *spd_data_ptr, size_t *spd_data_len)
{
struct region_device spd_rdev;
size_t spd_index = spd_info->spd_spec.spd_index;
printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index);
if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
die("spd.bin not found or incorrect index\n");
*spd_data_len = region_device_sz(&spd_rdev);
/* Memory leak is ok since we have memory mapped boot media */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
*spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev);
}
static void get_spd_data(const struct spd_info *spd_info,
uintptr_t *spd_data_ptr, size_t *spd_data_len)
{
if (spd_info->read_type == READ_SPD_MEMPTR) {
*spd_data_ptr = spd_info->spd_spec.spd_data_ptr_info.spd_data_ptr;
*spd_data_len = spd_info->spd_spec.spd_data_ptr_info.spd_data_len;
return;
}
if (spd_info->read_type == READ_SPD_CBFS) {
spd_read_from_cbfs(spd_info, spd_data_ptr, spd_data_len);
return;
}
}
static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg,
const struct mb_cfg *board_cfg,
bool half_populated)
{
memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor,
sizeof(mem_cfg->RcompResistor));
memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets,
sizeof(mem_cfg->RcompTarget));
memcpy(&mem_cfg->DqMapCpu2DramCh0, &board_cfg->dq_map[DDR_CH0],
sizeof(board_cfg->dq_map[DDR_CH0]));
memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0],
sizeof(board_cfg->dqs_map[DDR_CH0]));
memcpy(&mem_cfg->DqMapCpu2DramCh1, &board_cfg->dq_map[DDR_CH1],
sizeof(board_cfg->dq_map[DDR_CH1]));
memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1],
sizeof(board_cfg->dqs_map[DDR_CH1]));
memcpy(&mem_cfg->DqMapCpu2DramCh2, &board_cfg->dq_map[DDR_CH2],
sizeof(board_cfg->dq_map[DDR_CH2]));
memcpy(&mem_cfg->DqsMapCpu2DramCh2, &board_cfg->dqs_map[DDR_CH2],
sizeof(board_cfg->dqs_map[DDR_CH2]));
memcpy(&mem_cfg->DqMapCpu2DramCh3, &board_cfg->dq_map[DDR_CH3],
sizeof(board_cfg->dq_map[DDR_CH3]));
memcpy(&mem_cfg->DqsMapCpu2DramCh3, &board_cfg->dqs_map[DDR_CH3],
sizeof(board_cfg->dqs_map[DDR_CH3]));
if (half_populated)
return;
memcpy(&mem_cfg->DqMapCpu2DramCh4, &board_cfg->dq_map[DDR_CH4],
sizeof(board_cfg->dq_map[DDR_CH4]));
memcpy(&mem_cfg->DqsMapCpu2DramCh4, &board_cfg->dqs_map[DDR_CH4],
sizeof(board_cfg->dqs_map[DDR_CH4]));
memcpy(&mem_cfg->DqMapCpu2DramCh5, &board_cfg->dq_map[DDR_CH5],
sizeof(board_cfg->dq_map[DDR_CH5]));
memcpy(&mem_cfg->DqsMapCpu2DramCh5, &board_cfg->dqs_map[DDR_CH5],
sizeof(board_cfg->dqs_map[DDR_CH5]));
memcpy(&mem_cfg->DqMapCpu2DramCh6, &board_cfg->dq_map[DDR_CH6],
sizeof(board_cfg->dq_map[DDR_CH6]));
memcpy(&mem_cfg->DqsMapCpu2DramCh6, &board_cfg->dqs_map[DDR_CH6],
sizeof(board_cfg->dqs_map[DDR_CH6]));
memcpy(&mem_cfg->DqMapCpu2DramCh7, &board_cfg->dq_map[DDR_CH7],
sizeof(board_cfg->dq_map[DDR_CH7]));
memcpy(&mem_cfg->DqsMapCpu2DramCh7, &board_cfg->dqs_map[DDR_CH7],
sizeof(board_cfg->dqs_map[DDR_CH7]));
}
static void meminit_channels(FSP_M_CONFIG *mem_cfg,
const struct mb_cfg *board_cfg,
uintptr_t spd_data_ptr,
bool half_populated)
{
uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */
/* Channel 0 */
mem_cfg->DisableDimmMc0Ch0 = dimm_cfg;
mem_cfg->MemorySpdPtr00 = spd_data_ptr;
mem_cfg->MemorySpdPtr01 = 0;
/* Channel 1 */
mem_cfg->DisableDimmMc0Ch1 = dimm_cfg;
mem_cfg->MemorySpdPtr02 = spd_data_ptr;
mem_cfg->MemorySpdPtr03 = 0;
/* Channel 2 */
mem_cfg->DisableDimmMc0Ch2 = dimm_cfg;
mem_cfg->MemorySpdPtr04 = spd_data_ptr;
mem_cfg->MemorySpdPtr05 = 0;
/* Channel 3 */
mem_cfg->DisableDimmMc0Ch3 = dimm_cfg;
mem_cfg->MemorySpdPtr06 = spd_data_ptr;
mem_cfg->MemorySpdPtr07 = 0;
if (half_populated) {
printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__);
dimm_cfg = DISABLE_BOTH_DIMMS;
spd_data_ptr = 0;
}
/* Channel 4 */
mem_cfg->DisableDimmMc1Ch0 = dimm_cfg;
mem_cfg->MemorySpdPtr08 = spd_data_ptr;
mem_cfg->MemorySpdPtr09 = 0;
/* Channel 5 */
mem_cfg->DisableDimmMc1Ch1 = dimm_cfg;
mem_cfg->MemorySpdPtr10 = spd_data_ptr;
mem_cfg->MemorySpdPtr11 = 0;
/* Channel 6 */
mem_cfg->DisableDimmMc1Ch2 = dimm_cfg;
mem_cfg->MemorySpdPtr12 = spd_data_ptr;
mem_cfg->MemorySpdPtr13 = 0;
/* Channel 7 */
mem_cfg->DisableDimmMc1Ch3 = dimm_cfg;
mem_cfg->MemorySpdPtr14 = spd_data_ptr;
mem_cfg->MemorySpdPtr15 = 0;
meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
}
/* Initialize onboard memory configurations for lpddr4x */
void memcfg_init(FSP_M_CONFIG *mem_cfg,
const struct mb_cfg *board_cfg,
const struct spd_info *spd_info,
bool half_populated)
{
if (spd_info->read_type == READ_SMBUS) {
for (int i = 0; i < NUM_DIMM_SLOT; i++)
mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i];
meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
} else {
size_t spd_data_len = 0;
uintptr_t spd_data_ptr = 0;
memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable));
get_spd_data(spd_info, &spd_data_ptr, &spd_data_len);
mem_cfg->MemorySpdDataLen = spd_data_len;
meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
}
mem_cfg->ECT = board_cfg->ect;
mem_cfg->UserBd = board_cfg->UserBd;
}

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is created based on Intel Alder Lake Processor PCH Datasheet
* Document number: 621483
* Chapter number: 3
*/
#include <console/console.h>
#include <intelblocks/p2sb.h>
void p2sb_soc_get_sb_mask(uint32_t *ep_mask, size_t count)
{
uint32_t mask;
if (count != P2SB_EP_MASK_MAX_REG) {
printk(BIOS_ERR, "Unable to program EPMASK registers\n");
return;
}
/* Remove the host accessing right to PSF register range.
* Set p2sb PCI offset EPMASK5 [29, 28, 27, 26] to disable Sideband
* access for PCI Root Bridge.
*/
mask = (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26);
ep_mask[P2SB_EP_MASK_5_REG] = mask;
/*
* Set p2sb PCI offset EPMASK7 [31, 30] to disable Sideband
* access for Broadcast and Multicast.
*/
mask = (1 << 31) | (1 << 30);
ep_mask[P2SB_EP_MASK_7_REG] = mask;
}

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h>
#include <console/console.h>
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
#include <fsp/util.h>
#include <soc/intel/common/reset.h>
#include <soc/pci_devs.h>
void do_global_reset(void)
{
/* Ask CSE to do the global reset */
if (cse_request_global_reset(GLOBAL_RESET))
return;
/* global reset if CSE fail to reset */
pmc_global_reset_enable(1);
do_full_reset();
}
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}

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# SPDX-License-Identifier: GPL-2.0-only
romstage-y += fsp_params.c
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += pch.c
romstage-y += systemagent.c

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/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <fsp/util.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/mp_init.h>
#include <soc/gpio_soc_defs.h>
#include <soc/iomap.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
#include <string.h>
static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
const struct soc_intel_alderlake_dev_config *config)
{
unsigned int i;
uint32_t mask = 0;
const struct device *dev;
/*
* If IGD is enabled, set IGD stolen size to 60MB.
* Otherwise, skip IGD init in FSP.
*/
dev = pcidev_path_on_root(SA_DEVFN_IGD);
m_cfg->InternalGfx = is_dev_enabled(dev);
m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? IGD_SM_60MB : 0;
m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
m_cfg->SaGv = config->SaGv;
m_cfg->RMT = config->RMT;
/* CpuRatio Settings */
if (config->cpu_ratio_override)
m_cfg->CpuRatio = config->cpu_ratio_override;
else
/* Set CpuRatio to match existing MSR value */
m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])
mask |= (1 << i);
}
m_cfg->PcieRpEnableMask = mask;
memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
sizeof(config->PcieClkSrcUsage));
memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
m_cfg->PrmrrSize = get_prmrr_size();
m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;
/* UART Debug Log */
m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
if (CONFIG(DRIVERS_UART_8250IO))
m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
/* DP port config */
m_cfg->DdiPortAConfig = config->DdiPortAConfig;
m_cfg->DdiPortBConfig = config->DdiPortBConfig;
m_cfg->DdiPortAHpd = config->DdiPortAHpd;
m_cfg->DdiPortBHpd = config->DdiPortBHpd;
m_cfg->DdiPortCHpd = config->DdiPortCHpd;
m_cfg->DdiPort1Hpd = config->DdiPort1Hpd;
m_cfg->DdiPort2Hpd = config->DdiPort2Hpd;
m_cfg->DdiPort3Hpd = config->DdiPort3Hpd;
m_cfg->DdiPort4Hpd = config->DdiPort4Hpd;
m_cfg->DdiPortADdc = config->DdiPortADdc;
m_cfg->DdiPortBDdc = config->DdiPortBDdc;
m_cfg->DdiPortCDdc = config->DdiPortCDdc;
m_cfg->DdiPort1Ddc = config->DdiPort1Ddc;
m_cfg->DdiPort2Ddc = config->DdiPort2Ddc;
m_cfg->DdiPort3Ddc = config->DdiPort3Ddc;
m_cfg->DdiPort4Ddc = config->DdiPort4Ddc;
/* Image clock: disable all clocks for bypassing FSP pin mux */
memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn));
/* Enable Hyper Threading */
m_cfg->HyperThreading = 1;
/* Disable Lock PCU Thermal Management registers */
m_cfg->LockPTMregs = 0;
/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */
m_cfg->ChHashMask = 0x30CC;
/* Enable SMBus controller */
dev = pcidev_path_on_root(PCH_DEVFN_SMBUS);
m_cfg->SmbusEnable = is_dev_enabled(dev);
/* Set debug probe type */
m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
sizeof(m_cfg->PchHdaAudioLinkSspEnable));
memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
/* ISH */
dev = pcidev_path_on_root(PCH_DEVFN_ISH);
m_cfg->PchIshEnable = is_dev_enabled(dev);
/* Tcss USB */
dev = pcidev_path_on_root(SA_DEVFN_TCSS_XHCI);
m_cfg->TcssXhciEn = is_dev_enabled(dev);
dev = pcidev_path_on_root(SA_DEVFN_TCSS_XDCI);
m_cfg->TcssXdciEn = is_dev_enabled(dev);
/* TCSS DMA */
dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0);
m_cfg->TcssDma0En = is_dev_enabled(dev);
dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1);
m_cfg->TcssDma1En = is_dev_enabled(dev);
/* USB4/TBT */
dev = pcidev_path_on_root(SA_DEVFN_TBT0);
m_cfg->TcssItbtPcie0En = is_dev_enabled(dev);
dev = pcidev_path_on_root(SA_DEVFN_TBT1);
m_cfg->TcssItbtPcie1En = is_dev_enabled(dev);
dev = pcidev_path_on_root(SA_DEVFN_TBT2);
m_cfg->TcssItbtPcie2En = is_dev_enabled(dev);
dev = pcidev_path_on_root(SA_DEVFN_TBT3);
m_cfg->TcssItbtPcie3En = is_dev_enabled(dev);
/* Vt-D config */
/* Disable VT-d support for pre-QS platform */
m_cfg->VtdDisable = 1;
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
/* Skip CPU replacement check */
m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
/* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev);
}
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
const struct soc_intel_alderlake_dev_config *config;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
config = config_of_soc();
soc_memory_init_params(m_cfg, config);
mainboard_memory_init_params(mupd);
}
__weak void mainboard_memory_init_params(FSPM_UPD *mupd)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}

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src/soc/intel/alderlake/romstage/pch.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/smbus.h>
#include <soc/romstage.h>
void romstage_pch_init(void)
{
/* Program SMBus base address and enable it */
smbus_common_init();
}

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src/soc/intel/alderlake/romstage/romstage.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/romstage.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/cfg.h>
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
#include <memory_info.h>
#include <soc/intel/common/smbios.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
#include <string.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
}
__weak const char *mainboard_get_dram_part_num(size_t *len)
{
/* Default weak implementation, no need to override part number. */
return NULL;
}
/* Save the DIMM information for SMBIOS table 17 */
static void save_dimm_info(void)
{
int node, channel, dimm, dimm_max, index;
size_t hob_size;
const CONTROLLER_INFO *ctrlr_info;
const CHANNEL_INFO *channel_info;
const DIMM_INFO *src_dimm;
struct dimm_info *dest_dimm;
struct memory_info *mem_info;
const MEMORY_INFO_DATA_HOB *meminfo_hob;
const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID;
const uint8_t *serial_num;
const char *dram_part_num = NULL;
size_t dram_part_num_len;
/* Locate the memory info HOB, presence validated by raminit */
meminfo_hob = fsp_find_extension_hob_by_guid(
smbios_memory_info_guid,
&hob_size);
if (meminfo_hob == NULL || hob_size == 0) {
printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
return;
}
/*
* Allocate CBMEM area for DIMM information used to populate SMBIOS
* table 17
*/
mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
if (mem_info == NULL) {
printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
return;
}
memset(mem_info, 0, sizeof(*mem_info));
/* Allow mainboard to override DRAM part number. */
dram_part_num = mainboard_get_dram_part_num(&dram_part_num_len);
/* Save available DIMM information */
index = 0;
dimm_max = ARRAY_SIZE(mem_info->dimm);
for (node = 0; node < MAX_NODE; node++) {
ctrlr_info = &meminfo_hob->Controller[node];
for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
channel_info = &ctrlr_info->ChannelInfo[channel];
if (channel_info->Status != CHANNEL_PRESENT)
continue;
for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
src_dimm = &channel_info->DimmInfo[dimm];
dest_dimm = &mem_info->dimm[index];
if (src_dimm->Status != DIMM_PRESENT)
continue;
/* If there is no DRAM part number overridden by
* mainboard then use original one. */
if (!dram_part_num) {
dram_part_num_len = sizeof(src_dimm->ModulePartNum);
dram_part_num = (const char *)
&src_dimm->ModulePartNum[0];
}
uint8_t memProfNum = meminfo_hob->MemoryProfile;
serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL;
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
src_dimm->DimmCapacity,
meminfo_hob->MemoryType,
meminfo_hob->ConfiguredMemoryClockSpeed,
src_dimm->RankInDimm,
channel_info->ChannelId,
src_dimm->DimmId,
dram_part_num,
dram_part_num_len,
serial_num,
meminfo_hob->DataWidth,
meminfo_hob->VddVoltage[memProfNum],
meminfo_hob->EccSupport,
src_dimm->MfgId,
src_dimm->SpdModuleType);
index++;
}
}
}
mem_info->dimm_cnt = index;
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
}
void mainboard_romstage_entry(void)
{
bool s3wake;
struct chipset_power_state *ps = pmc_get_power_state();
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
/* Perform PCH init */
romstage_pch_init();
/* Initialize HECI interface */
heci_init(HECI1_BASE_ADDRESS);
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);
pmc_set_disb();
if (!s3wake)
save_dimm_info();
}

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src/soc/intel/alderlake/romstage/systemagent.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This file is created based on Intel Alder Lake Processor SA Datasheet
* Document number: 619503
* Chapter number: 3
*/
#include <intelblocks/systemagent.h>
#include <soc/iomap.h>
#include <soc/romstage.h>
#include <soc/systemagent.h>
void systemagent_early_init(void)
{
static const struct sa_mmio_descriptor soc_fixed_pci_resources[] = {
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
};
static const struct sa_mmio_descriptor soc_fixed_mch_resources[] = {
{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
};
/* Set Fixed MMIO address into PCI configuration space */
sa_set_pci_bar(soc_fixed_pci_resources,
ARRAY_SIZE(soc_fixed_pci_resources));
/* Set Fixed MMIO address into MCH base address */
sa_set_mch_bar(soc_fixed_mch_resources,
ARRAY_SIZE(soc_fixed_mch_resources));
/* Enable PAM registers */
enable_pam_region();
}