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mainboard/intel/d510mo: Licence fixes and azalia verb table 

Azalia verb table replicated from vendor bios.
Licence headers added where appropriate.

Change-Id: I29e4fe433dee6c5f30fe36055fc9a8bf2062fef5
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12621
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Damien Zammit 2015-12-02 14:03:02 +11:00 committed by Martin Roth
parent 546f29dbf1
commit 2950cd2de1
3 changed files with 51 additions and 4 deletions
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15
src/mainboard/intel/d510mo/cstates.c
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@ -1,3 +1,18 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <arch/x86/include/arch/acpigen.h>

36
src/mainboard/intel/d510mo/hda_verb.c
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@ -1,7 +1,39 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[0] = {};
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0662,
0x8086d618, // Subsystem ID
0x0000000a, // Number of entries
const u32 pc_beep_verbs[0] = {};
/* Pin Widget Verb Table */
AZALIA_PIN_CFG(0, 0x14, 0x01014410),
AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
AZALIA_PIN_CFG(0, 0x19, 0x02a19841),
AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
AZALIA_PIN_CFG(0, 0x1b, 0x02214420),
AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x4015c603),
AZALIA_PIN_CFG(0, 0x1e, 0x99430130),
};
const u32 pc_beep_verbs[] = {
};
AZALIA_ARRAY_SIZES;

4
src/mainboard/intel/d510mo/romstage.c
View File

@ -125,9 +125,9 @@ void main(unsigned long bist)
post_code(0x30);
printk(BIOS_DEBUG, "Start native raminit\n");
printk(BIOS_DEBUG, "Initializing memory\n");
sdram_initialize(0, spd_addrmap);
printk(BIOS_DEBUG, "Native raminit done\n");
printk(BIOS_DEBUG, "Memory initialized\n");
post_code(0x31);
ram_check(0x200000,0x300000);