From 2962d1e971316e342554bcc2253a617e12ff8acc Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 19 Nov 2014 12:01:39 -0600 Subject: [PATCH] tegra132: always bring up PLLD The kernel does not correctly function without PLLD being enabled. Additionally, PLLD can be the source for other clocks in the system. Therefore, initialize PLLD to 300MHz unconditionally at BS_DEV_INIT time in ramstage. BUG=chrome-os-partner:33825 BRANCH=None TEST=Built and booted ryu with display coming up both in dev mode as well as normal mode. Change-Id: Ib2a60bb9aafc03dc23aa932a480184d87f677c65 Signed-off-by: Patrick Georgi Original-Commit-Id: 4c49f964b55c3c33d03b95363277b262b679e740 Original-Change-Id: Ic5905e25051a042cea5010b8c6d61b1fb89a0a81 Original-Signed-off-by: Aaron Durbin Original-Reviewed-on: https://chromium-review.googlesource.com/230774 Original-Reviewed-by: Tom Warren Original-Reviewed-by: Furquan Shaikh Original-Tested-by: Sean Paul Reviewed-on: http://review.coreboot.org/9525 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/soc/nvidia/tegra132/soc.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c index b91260eef3..a77ffbbff4 100644 --- a/src/soc/nvidia/tegra132/soc.c +++ b/src/soc/nvidia/tegra132/soc.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -143,3 +144,20 @@ static const struct cpu_driver driver __cpu_driver = { .ops = &cpu_dev_ops, .id_table = ids, }; + +static void enable_plld(void *unused) +{ + /* + * Configure a conservative 300MHz clock for PLLD. The kernel cannot + * handle PLLD not being configured so enable PLLD unconditionally + * with a default clock rate. + */ + clock_configure_plld(300 * MHz); +} + +/* + * The PLLD being enabled is done at BS_DEV_INIT time because mainboard_init() + * is the first thing called. This ensures PLLD is up and functional before + * anything that mainboard can do that implicitly relies on PLLD. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, enable_plld, NULL);