vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155
This CL implements below changes: 1) Update FSP-M and FSP-S header files as per FSP release version 1155. 2) Update the PcdSerialIoUartNumber reference in fsp_params.c with SerialIoUartDebugControllerNumber. Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -50,7 +50,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
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m_cfg->PcieRpEnableMask = mask;
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m_cfg->PrmrrSize = config->PrmrrSize;
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m_cfg->EnableC6Dram = config->enable_c6dram;
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#if CONFIG(SOC_INTEL_COMETLAKE)
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m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
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#else
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m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE;
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#endif
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/*
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* PcdDebugInterfaceFlags
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* This config will allow coreboot to pass information to the FSP
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