include/cpu/x86: Add STM Support
Addtions to include/cpu/x86 include for STM support. Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: ron minnich <rminnich@gmail.com>
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@ -30,6 +30,10 @@
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#define IA32_BIOS_SIGN_ID 0x8b
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#define IA32_MPERF 0xe7
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#define IA32_APERF 0xe8
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/* STM */
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#define IA32_SMM_MONITOR_CTL_MSR 0x9B
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#define SMBASE_RO_MSR 0x98
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#define IA32_SMM_MONITOR_VALID (1<<0)
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#define IA32_MCG_CAP 0x179
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#define MCG_CTL_P (1 << 3)
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#define MCA_BANKS_MASK 0xff
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@ -48,6 +52,8 @@
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#define IA32_PAT 0x277
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#define IA32_MC0_CTL 0x400
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#define IA32_MC0_STATUS 0x401
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#define IA32_VMX_BASIC_MSR 0x480
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#define IA32_VMX_MISC_MSR 0x485
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#define MCA_STATUS_HI_VAL (1UL << (63 - 32))
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#define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
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#define MCA_STATUS_HI_UC (1UL << (61 - 32))
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@ -64,6 +64,9 @@ extern unsigned char _binary_smm_end[];
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struct smm_runtime {
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u32 smbase;
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u32 save_state_size;
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u32 num_cpus;
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/* STM's 32bit entry into SMI handler */
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u32 start32_offset;
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/* The apic_id_to_cpu provides a mapping from APIC id to CPU number.
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* The CPU number is indicated by the index into the array by matching
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* the default APIC id and value at the index. The stub loader
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