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soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT 

Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is only used on `starlabs/starbook` which
selects D3COLD_SUPPORT so the UPDs will not change.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2023-04-17 20:28:01 +01:00 committed by Lean Sheng Tan
parent 648ff9268f
commit 2980e317e3
4 changed files with 1 additions and 5 deletions
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1
src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
View File

@ -19,7 +19,6 @@ chip soc/intel/tigerlake
register "CnviBtAudioOffload" = "1" register "CnviBtAudioOffload" = "1"
register "enable_c6dram" = "1" register "enable_c6dram" = "1"
register "SaGv" = "SaGv_Enabled" register "SaGv" = "SaGv_Enabled"
register "TcssD3ColdDisable" = "1"
# FSP Silicon # FSP Silicon
# Serial I/O # Serial I/O

1
src/mainboard/starlabs/starbook/variants/tgl/devtree.c
View File

@ -60,7 +60,6 @@ void devtree_update(void)
if (get_uint_option("thunderbolt", 1) == 0) { if (get_uint_option("thunderbolt", 1) == 0) {
cfg->UsbTcPortEn = 0; cfg->UsbTcPortEn = 0;
cfg->TcssXhciEn = 0; cfg->TcssXhciEn = 0;
cfg->TcssD3ColdDisable = 0;
tbt_pci_dev->enabled = 0; tbt_pci_dev->enabled = 0;
tbt_dma_dev->enabled = 0; tbt_dma_dev->enabled = 0;
} }

2
src/soc/intel/tigerlake/chip.h
View File

@ -148,8 +148,6 @@ struct soc_intel_tigerlake_config {
/* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */
uint8_t TcssD3HotDisable; uint8_t TcssD3HotDisable;
/* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */
uint8_t TcssD3ColdDisable;
/* Enable DPTF support */ /* Enable DPTF support */
int dptf_enable; int dptf_enable;

2
src/soc/intel/tigerlake/fsp_params.c
View File

@ -327,7 +327,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
if (cpu_id == CPUID_TIGERLAKE_A0) if (cpu_id == CPUID_TIGERLAKE_A0)
params->D3ColdEnable = 0; params->D3ColdEnable = 0;
else else
params->D3ColdEnable = !config->TcssD3ColdDisable; params->D3ColdEnable = CONFIG(D3COLD_SUPPORT);
params->UsbTcPortEn = config->UsbTcPortEn; params->UsbTcPortEn = config->UsbTcPortEn;
params->TcssAuxOri = config->TcssAuxOri; params->TcssAuxOri = config->TcssAuxOri;