diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index bc81602747..e6acfc8bbc 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -61,19 +61,8 @@ DefinitionBlock (
 			Name(_STA, 0x0B)
 		}
 
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <pci_int.asl>
-
-		/* Describe the devices in the Southbridge */
-		#include <soc_fch.asl>
+		/* Describe the SOC */
+		#include <soc.asl>
 
 	} /* End \_SB scope */
 
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 885dd8dce0..ded0dc8779 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -61,19 +61,8 @@ DefinitionBlock (
 			Name(_UID, 0xAA)
 		}
 
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <pci_int.asl>
-
-		/* Describe the devices in the Southbridge */
-		#include <soc_fch.asl>
+		/* Describe the SOC */
+		#include <soc.asl>
 
 	} /* End \_SB scope */
 
diff --git a/src/soc/amd/stoneyridge/acpi/soc_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl
similarity index 100%
rename from src/soc/amd/stoneyridge/acpi/soc_fch.asl
rename to src/soc/amd/stoneyridge/acpi/sb_fch.asl
diff --git a/src/soc/amd/stoneyridge/acpi/fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
similarity index 100%
rename from src/soc/amd/stoneyridge/acpi/fch.asl
rename to src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl
new file mode 100644
index 0000000000..d7772948ef
--- /dev/null
+++ b/src/soc/amd/stoneyridge/acpi/soc.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device(PCI0) {
+	/* Describe the AMD Northbridge */
+	#include "northbridge.asl"
+
+	/* Describe the AMD Fusion Controller Hub */
+	#include "sb_pci0_fch.asl"
+}
+
+/* Describe PCI INT[A-H] for the Southbridge */
+#include "pci_int.asl"
+
+/* Describe the devices in the Southbridge */
+#include "sb_fch.asl"