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mb/google/skyrim/var/frostflow: Update DPTC and STT settings 

According to thermal_table_0215, adjust DPTC and STT settings.

BRANCH=none
BUG=b:257149501
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frank Wu 2023-02-17 15:09:06 +08:00 committed by Felix Held
parent 2809507ca7
commit 29863f6cf2
1 changed files with 23 additions and 0 deletions
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23
src/mainboard/google/skyrim/variants/frostflow/overridetree.cb
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@ -147,4 +147,27 @@ chip soc/amd/mendocino
end
end # UART1
# Set Package Power Parameters
register "thermctl_limit_degreeC" = "90"
# STT settings
register "stt_control" = "1"
register "stt_pcb_sensor_count" = "2"
register "stt_error_coeff" = "0x21"
register "stt_error_rate_coefficient" = "0x2666"
register "stt_min_limit" = "15000"
register "stt_skin_temp_apu" = "0x3000"
# STT default mode
register "stt_m1" = "0xfed2"
register "stt_m2" = "0x5f9"
register "stt_c_apu" = "0xfbf8"
register "stt_alpha_apu" = "0x4ccd"
# STT tablet mode
register "stt_m1_tablet" = "0x208"
register "stt_m2_tablet" = "0x1f5"
register "stt_c_apu_tablet" = "0xa2"
register "stt_alpha_apu_tablet" = "0x199a"
end # chip soc/amd/mendocino