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Improve error handling and make RCONF_DEFAULT_MSR address be a constant. 

Also, move a big code comment to the top of enable_flash_cs5536().

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Mart Raudsepp 2008-02-08 10:10:57 +00:00 committed by Uwe Hermann
parent 99062ae5ad
commit 2995cc69f7
1 changed files with 52 additions and 26 deletions
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78
util/flashrom/chipset_enable.c
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@ -226,71 +226,97 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
return 0;
}
/**
* Geode systems write protect the BIOS via RCONFs (cache settings similar
* to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
* writing to MSRs, however requires instructions rdmsr/wrmsr, which are
* ring0 privileged instructions so only the kernel can do the read/write.
* This function, therefore, requires that the msr kernel module be loaded
* to access these instructions from user space using device /dev/cpu/0/msr.
*
* This hard-coded location could have potential problems on SMP machines
* since it assumes cpu0, but it is safe on the Geode which is not SMP.
*
* Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
* To enable write to NOR Boot flash for the benefit of systems that have such
* a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
*
* This is probably not portable beyond Linux.
*/
static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
{
#define MSR_NORF_CTL 0x51400018
#define MSR_RCONF_DEFAULT 0x1808
#define MSR_NORF_CTL 0x51400018
int fd_msr;
unsigned char buf[8];
unsigned int addr = 0x1808;
/* Geode systems write protect the BIOS via RCONFs (cache
* settings similar to MTRRs). To unlock, change MSR 0x1808
* top byte to 0x22. Reading and writing to msr, however
* requires instructions rdmsr/wrmsr, which are ring0 privileged
* instructions so only the kernel can do the read/write. This
* function, therefore, requires that the msr kernel module be
* loaded to access these instructions from user space using
* device /dev/cpu/0/msr. This hard-coded driver location
* could have potential problems on SMP machines since it
* assumes cpu0, but it is safe on the Geode which is not SMP.
*
* Geode systems also write protect the NOR flash chip itself
* via MSR_NORF_CTL. To enable write to NOR Boot flash for the
* benefit of systems that have such a setup, raise
* MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
*
* This is probably not portable beyond Linux.
*/
fd_msr = open("/dev/cpu/0/msr", O_RDWR);
if (!fd_msr) {
perror("open msr");
return -1;
}
lseek64(fd_msr, (off64_t) addr, SEEK_SET);
read(fd_msr, buf, 8);
if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
perror("lseek64");
close(fd_msr);
return -1;
}
if (read(fd_msr, buf, 8) != 8) {
perror("read");
close(fd_msr);
return -1;
}
printf("Enabling Geode MSR to write to flash.\n");
if (buf[7] != 0x22) {
buf[7] &= 0xfb;
lseek64(fd_msr, (off64_t) addr, SEEK_SET);
if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
perror("lseek64");
close(fd_msr);
return -1;
}
if (write(fd_msr, buf, 8) < 0) {
perror("msr write");
printf("Cannot write to MSR. Did you run 'modprobe msr'?\n");
close(fd_msr);
return -1;
}
}
lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET);
if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
perror("lseek64");
close(fd_msr);
return -1;
}
if (read(fd_msr, buf, 8) != 8) {
perror("read msr");
close(fd_msr);
return -1;
}
/* Raise WE_CS3 bit. */
buf[0] |= 0x08;
lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET);
if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
perror("lseek64");
close(fd_msr);
return -1;
}
if (write(fd_msr, buf, 8) < 0) {
perror("msr write");
printf("Cannot write to MSR. Did you run 'modprobe msr'?\n");
close(fd_msr);
return -1;
}
close(fd_msr);
#undef MSR_RCONF_DEFAULT
#undef MSR_NORF_CTL
return 0;
}