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mb/intel/latest mainboards: Get rid of power button device in coreboot 

Refer to commit d7b88dc (mb/google/x86-boards: Get rid of power button
device in coreboot)

This change gets rid of the generic hardware power button from all
intel mainboards and relies completely on the fixed hardware power
button.

Change-Id: I8f9d73048041d42d809750fdb52092f40ab8f11f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2020-10-10 19:41:19 +05:30
parent bbb8123d66
commit 299689c85f
10 changed files with 0 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/mainboard/intel/icelake_rvp/acpi/mainboard.asl
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@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(EC_GOOGLE_CHROMEEC)
Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
}
#endif

4
src/mainboard/intel/icelake_rvp/dsdt.asl
View File

@ -46,8 +46,4 @@ DefinitionBlock(
#endif #endif
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
} }

11
src/mainboard/intel/jasperlake_rvp/acpi/mainboard.asl
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(EC_GOOGLE_CHROMEEC)
Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
}
#endif

4
src/mainboard/intel/jasperlake_rvp/dsdt.asl
View File

@ -46,8 +46,4 @@ DefinitionBlock(
#endif #endif
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */
#include "acpi/mainboard.asl"
} }

11
src/mainboard/intel/kblrvp/acpi/mainboard.asl
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(EC_GOOGLE_CHROMEEC)
Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
}
#endif

3
src/mainboard/intel/kblrvp/dsdt.asl
View File

@ -41,7 +41,4 @@ DefinitionBlock(
#endif #endif
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
} }

9
src/mainboard/intel/kunimitsu/acpi/mainboard.asl
View File

@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
}

3
src/mainboard/intel/kunimitsu/dsdt.asl
View File

@ -33,7 +33,4 @@ DefinitionBlock(
#include <vendorcode/google/chromeos/acpi/chromeos.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
// Mainboard specific
#include "acpi/mainboard.asl"
} }

11
src/mainboard/intel/tglrvp/acpi/mainboard.asl
View File

@ -1,11 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(EC_GOOGLE_CHROMEEC)
Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
}
#endif

3
src/mainboard/intel/tglrvp/dsdt.asl
View File

@ -49,9 +49,6 @@ DefinitionBlock(
#include <southbridge/intel/common/acpi/sleepstates.asl> #include <southbridge/intel/common/acpi/sleepstates.asl>
/* Mainboard specific */
#include "acpi/mainboard.asl"
/* Camera */ /* Camera */
#include "acpi/mipi_camera.asl" #include "acpi/mipi_camera.asl"
} }