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mb/google/puff: Increase DPTF parameters for faffy 

Update critical and passive policy for TSR0.

BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
David Wu 2020-09-08 15:30:29 +08:00 committed by Edward O'Callaghan
parent 8e0f9f30f6
commit 299cb4bb8a
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/hatch/variants/faffy/overridetree.cb
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@ -281,11 +281,11 @@ chip soc/intel/cannonlake
chip drivers/intel/dptf
## Passive Policy
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 63, 5000)"
register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)"
## Critical Policy
register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)"
## Power Limits Control
# 10-15W PL1 in 200mW increments, avg over 28-32s interval