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soc/intel/broadwell: Add ECC config reporting 

This has been taken from Haswell, and is just to reduce differences.

Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-10-13 23:32:55 +02:00
parent 162a737599
commit 29a52c8308
1 changed files with 8 additions and 1 deletions
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9
src/soc/intel/broadwell/romstage/raminit.c
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@ -21,6 +21,13 @@
#include <soc/romstage.h> #include <soc/romstage.h>
#include <soc/systemagent.h> #include <soc/systemagent.h>
static const char *const ecc_decoder[] = {
"inactive",
"active on IO",
"disabled on IO",
"active",
};
/* /*
* Dump in the log memory controller configuration as read from the memory * Dump in the log memory controller configuration as read from the memory
* controller registers. * controller registers.
@ -43,7 +50,7 @@ static void report_memory_config(void)
const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); const u32 ch_conf = MCHBAR32(MAD_DIMM(i));
printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
printk(BIOS_DEBUG, " enhanced interleave mode %s\n", printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
((ch_conf >> 22) & 1) ? "on" : "off"); ((ch_conf >> 22) & 1) ? "on" : "off");