mb/google/brya/gaelin: Configure GPIO settings
Override GPIO pad configuration based on the latest gaelin schematic. BUG=b:249000573 BRANCH=firmware-brya-14505.B TEST=FW_NAME=emerge-brask coreboot Change-Id: I649ac5131393008787cbb403fc64b914de23312b Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
This commit is contained in:
Raymond Chung
Felix Held
parent
c6529c7c0a
commit
29bc20f996
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@ -1 +1,6 @@
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bootblock-y += gpio.c
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romstage-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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@ -0,0 +1,185 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <soc/gpio.h>
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/* Pad configuration in ramstage */
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static const struct pad_config override_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* A17 : DISP_MISCC ==> EN_FCAM_PWR */
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PAD_CFG_GPO(GPP_A17, 0, DEEP),
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/* A19 : DDSP_HPD1 ==> NC */
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PAD_NC(GPP_A19, NONE),
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/* A20 : DDSP_HPD2 ==> NC */
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PAD_NC(GPP_A20, NONE),
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/* A21 : DDPC_CTRCLK ==> NC */
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PAD_NC(GPP_A21, NONE),
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/* A22 : DDPC_CTRLDATA ==> NC */
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PAD_NC(GPP_A22, NONE),
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/* B2 : VRALERT# ==> NC */
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PAD_NC(GPP_B2, NONE),
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/* B3 : PROC_GP2 ==> NC */
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PAD_NC(GPP_B3, NONE),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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/* B7 : ISH_12C1_SDA ==> NC */
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PAD_NC(GPP_B7, NONE),
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/* B8 : ISH_I2C1_SCL ==> NC */
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PAD_NC(GPP_B8, NONE),
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/* C6 : SML1CLK ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C6, 0, DEEP),
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/* C7 : SML1DATA ==> USI_INT_L */
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PAD_CFG_GPO(GPP_C7, 0, DEEP),
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/* D0 : ISH_GP0 ==> NC */
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PAD_NC(GPP_D0, NONE),
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/* D1 : ISH_GP1 ==> NC */
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PAD_NC(GPP_D1, NONE),
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/* D2 : ISH_GP2 ==> NC */
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PAD_NC(GPP_D2, NONE),
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/* D3 : ISH_GP3 ==> NC */
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PAD_NC(GPP_D3, NONE),
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/* D8 : SRCCLKREQ3# ==> NC */
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PAD_NC(GPP_D8, NONE),
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/* D9 : ISH_SPI_CS# ==> NC */
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PAD_NC(GPP_D9, NONE),
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/* D11 : ISH_SPI_MISO ==> NC */
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PAD_NC(GPP_D11, NONE),
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/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
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PAD_NC(GPP_D12, NONE),
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/* D17 : UART1_RXD ==> NC */
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PAD_NC(GPP_D17, NONE),
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/* D18 : UART1_TXD ==> NC */
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PAD_NC(GPP_D18, NONE),
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/* E4 : SATA_DEVSLP0 ==> USB_A0_RT_RST_ODL */
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PAD_CFG_GPO(GPP_E4, 1, DEEP),
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/* E5 : SATA_DEVSLP1 ==> USB_A1_RT_RST_ODL */
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PAD_CFG_GPO(GPP_E5, 1, DEEP),
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/* E7 : PROC_GP1 ==> EN_MIC_PWR */
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PAD_CFG_GPO(GPP_E7, 0, DEEP),
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/* E14 : DDSP_HPDA ==> EDP_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* E18 : DDP1_CTRLCLK ==> NC */
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PAD_NC(GPP_E18, NONE),
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/* E20 : DDP2_CTRLCLK ==> NC */
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PAD_NC(GPP_E20, NONE),
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/* F11 : THC1_SPI2_CLK ==> NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : GSXDOUT ==> NC */
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PAD_NC(GPP_F12, NONE),
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/* F13 : GSXDOUT ==> NC */
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PAD_NC(GPP_F13, NONE),
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/* F14 : GSXDIN ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_F14, 1, DEEP),
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/* F15 : GSXSRESET# ==> NC */
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PAD_NC(GPP_F15, NONE),
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/* F16 : GSXCLK ==> NC */
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PAD_NC(GPP_F16, NONE),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* H12 : I2C7_SDA ==> NC */
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PAD_NC(GPP_H12, NONE),
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/* H13 : I2C7_SCL ==> NC */
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PAD_NC(GPP_H13, NONE),
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/* R6 : I2S2_TXD ==> NC */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S2_RXD ==> NC */
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PAD_NC(GPP_R7, NONE),
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/* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
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PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
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/* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */
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PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
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/* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */
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PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
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/* S6 : SNDW3_CLK ==> DMIC_CLK1_R */
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PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
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/* S7 : SNDW3_DATA ==> DMIC_DATA1_R */
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PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 0, DEEP),
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/* E15 : RSVD_TP ==> PCH_WP_OD */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
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/* F14 : GSXDIN ==> EN_PP3300_SSD */
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PAD_CFG_GPO(GPP_F14, 1, DEEP),
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/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
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PAD_CFG_GPI(GPP_F18, NONE, DEEP),
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/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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/* CPU PCIe VGPIO for PEG60 */
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
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PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* B4 : PROC_GP3 ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_B4, 1, DEEP),
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};
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const struct pad_config *variant_gpio_override_table(size_t *num)
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{
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*num = ARRAY_SIZE(override_gpio_table);
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return override_gpio_table;
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}
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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const struct pad_config *variant_romstage_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(romstage_gpio_table);
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return romstage_gpio_table;
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}
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