From 29c3e367da8f80becacb66193d044f90b49bf0c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 16 Apr 2014 16:30:00 +0300 Subject: [PATCH] AMD cimx sb700/sb800/sb900: Fix NODE_PCI and use of MAX_PHYSICAL_CPUS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Match the definition of NODE_PCI() with get_node_pci(), so romstage and ramstage agree of the PCI BDFs for nodes. Note that all board have CONFIG_CDB = 0x18 and the maximum for nodes = 8, so we always have (CONFIG_CDB + x) < 32. Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/5536 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/southbridge/amd/cimx/sb700/reset.c | 6 +----- src/southbridge/amd/cimx/sb800/reset.c | 6 +----- src/southbridge/amd/cimx/sb900/reset.c | 6 +----- 3 files changed, 3 insertions(+), 15 deletions(-) diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index 16c56a2c83..a00fc15653 100644 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -26,11 +26,7 @@ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif +#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) static inline void set_bios_reset(void) { diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 16c56a2c83..a00fc15653 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -26,11 +26,7 @@ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif +#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) static inline void set_bios_reset(void) { diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 16c56a2c83..a00fc15653 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -26,11 +26,7 @@ #define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) -#if CONFIG_MAX_PHYSICAL_CPUS > 32 -#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) -#else -#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) -#endif +#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) static inline void set_bios_reset(void) {